Patents by Inventor Hyung-ik Lee

Hyung-ik Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9590121
    Abstract: An optoelectronic device includes a first electrode and a second electrode facing each other, a photoelectric conversion layer between the first electrode and the second electrode, and a buffer layer between at least one of the photoelectric conversion layer and the first electrode, and the photoelectric conversion layer and the second electrode, the buffer layer including one of MoOx1 (2.58?x1<3.0), ZnOx2 (1.0?x2<2.0), TiOx3 (1.5?x3<2.0), VOx4 (1.5?x4<2.0), TaOx5 (1.0?x5<2.5), WOx6 (2.0<x6<3.0), and a combination thereof.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong Heon Kim, Dongjin Yun, Sung Heo, Kyu Sik Kim, Satoh Ryuichi, Gyeongsu Park, Hyung-Ik Lee
  • Publication number: 20160233351
    Abstract: An optoelectronic device includes a first electrode and a second electrode facing each other, a photoelectric conversion layer between the first electrode and the second electrode, and a buffer layer between at least one of the photoelectric conversion layer and the first electrode, and the photoelectric conversion layer and the second electrode, the buffer layer including one of MoOx1 (2.58?x1<3.0), ZnOx2 (1.0?x2<2.0), TiOx3 (1.5?x3<2.0), VOx4 (1.5?x4<2.0), TaOx5 (1.0?x5<2.5), WOx6 (2.0<x6<3.0), and a combination thereof.
    Type: Application
    Filed: June 19, 2015
    Publication date: August 11, 2016
    Inventors: Seong Heon KIM, Dongjin YUN, Sung HEO, Kyu Sik KIM, Satoh RYUICHI, Gyeongsu PARK, Hyung-Ik LEE
  • Patent number: 8835257
    Abstract: A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Pil Kim, Hyung-Ik Lee, Woo-Sung Jeon, Ki-Hong Kim, Jung-Yun Won, In-Sun Jung
  • Patent number: 8440527
    Abstract: A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: May 14, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Chul Yoo, Eun-Ha Lee, Hyung-Ik Lee, Ki-Hyun Hwang, Sung Heo, Han-Mei Choi, Yong-Koo Kyoung, Byong-Ju Kim
  • Patent number: 8324043
    Abstract: Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-bum Kim, Si-young Choi, Hyung-ik Lee, Ki-hong Kim, Yong-koo Kyoung
  • Patent number: 8294198
    Abstract: A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Chul Yoo, Eun-Ha Lee, Byong-Ju Kim, Hyung-Ik Lee, Sung Heo, Han-Mei Choi, Chan-Hee Park, Ki-Hyun Hwang
  • Publication number: 20120231605
    Abstract: A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode.
    Type: Application
    Filed: December 6, 2011
    Publication date: September 13, 2012
    Inventors: Young-Pil KIM, Hyung-Ik Lee, Woo-Sung Jeon, Ki-Hong Kim, Jung-Yun Won, In-Sun Jung
  • Publication number: 20120178231
    Abstract: Methods for fabricating a metal silicide layer and for fabricating a semiconductor device having such a metal silicide layer are provided wherein, in an embodiment, the method includes the steps of forming a metal layer on a substrate, performing a first thermal process on the substrate to allow the substrate and the metal layer to react with react other to form a first pre-metal silicide layer, removing an unreacted portion of the metal layer, and performing a second thermal process on the substrate to change the first pre-metal silicide layer into a second pre-metal silicide layer and then to melt the second pre-metal silicide layer to change the second pre-metal silicide layer into a metal silicide layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Bum Kim, Young-Pil Kim, Hyung-Ik Lee, Ki-Hong Kim, Eun-Ha Lee, Jung-Yun Won, Benayad Anass
  • Publication number: 20120003799
    Abstract: Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.
    Type: Application
    Filed: September 8, 2011
    Publication date: January 5, 2012
    Inventors: Jin-bum Kim, Si-young Choi, Hyung-Ik Lee, Ki-hong Kim, Yong-koo Kyoung
  • Patent number: 8043595
    Abstract: Provided are a mesoporous carbon containing at least one heteroatom boron and phosphorus, a manufacturing method thereof, and a fuel cell using the same. The mesoporous carbon contains a heteroatom such as boron and phosphorous to reduce sheet resistance, and thus can efficiently transfer electric energy. Such a mesoporous carbon can be used as a conductive material of electrodes for fuel cells. When the mesoporous carbon is used as a support for catalysts of electrodes, a supported catalyst containing the support can be used to manufacture a fuel cell having high efficiency.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: October 25, 2011
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Chan-ho Pak, Sang-hoon Joo, Hyuk Chang, Ji-man Kim, Hyung-Ik Lee
  • Patent number: 8039902
    Abstract: Semiconductor devices include a substrate having first and second active regions; a P-channel transistor associated with the first active region and including at least one of source and drain regions; an N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; first and second contact pad layers each including silicon (Si) and SiGe epitaxial layers on the source and drain regions the SiGe epitaxial layers being sequentially stacked on the Si epitaxial layers; an interlayer insulating film; a first metal silicide film on the SiGe epitaxial layer of the P-channel transistor and a second metal silicide film on the Si epitaxial layer of the N-channel transistor; and contact plugs on the first and second metal silicide films.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-bum Kim, Si-young Choi, Hyung-ik Lee, Ki-hong Kim, Yong-koo Kyoung
  • Patent number: 7867941
    Abstract: A sulfur-containing mesoporous carbon that has mesopores with an average diameter of 2 to 10 nm, a method of preparing the same, a catalyst containing the mesoporous carbon as a catalyst support, and a fuel cell using the catalyst in which the sulfur-containing mesoporous carbon has a good affinity for and adhesion to catalyst particles so as to strongly support the catalyst particles due to the sulfur atoms substituting for carbons in an OMC carbon skeleton structure. The growth of metal catalyst particles is prevented when heat-treating the metal catalyst particles. The catalyst using the sulfur-containing mesoporous carbon can be applied to a fuel cell to prevent a reduction in catalytic activity due to increased particle size by an accumulation of catalyst particles. The catalyst containing the sulfur-containing mesoporous carbon as a catalyst support can be used to manufacture a fuel cell having an improved performance.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 11, 2011
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sang Hoon Joo, Chan-ho Pak, Hyuk Chang, Ji-man Kim, Hyung-ik Lee
  • Publication number: 20110001183
    Abstract: A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.
    Type: Application
    Filed: March 5, 2010
    Publication date: January 6, 2011
    Inventors: Dong-Chul Yoo, Eun-Ha Lee, Hyung-Ik Lee, Ki-Hyun Hwang, Sung Heo, Han-Mei Choi, Yong-Koo Kyoung, Byong-Ju Kim
  • Patent number: 7854913
    Abstract: A mesoporous carbon is prepared by mixing a carbon precursor, an acid, and a solvent to obtain a carbon precursor mixture; impregnating an ordered mesoporous silica (OMS) with the carbon precursor mixture; carbonizing the impregnated OMS at 800 to 1300° C. by irradiating microwave energy with a power of 100 to 2000 W thereon to form an OMS-carbon composite; and removing the mesoporous silica from the OMS-carbon composite. The method of preparing a mesoporous carbon can significantly reduce a carbonization time by carbonizing a carbon precursor using microwave energy in a silica template compared to a conventional method using a heat treatment. A supported catalyst and a fuel cell include the mesoporous carbon.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 21, 2010
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Sang-hoon Joo, Chan-ho Pak, Hyuk Chang, Ji-man Kim, Hyung-ik Lee
  • Publication number: 20100200907
    Abstract: A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 12, 2010
    Inventors: Dong Chul Yoo, Eun-Ha Lee, Byong-Ju Kim, Hyung-Ik Lee, Sung Heo, Han-Mei Choi, Chan-Hee Park, Ki-Hyun Hwang
  • Publication number: 20100123198
    Abstract: Provided are semiconductor devices having low resistance contacts and methods of manufacturing the same.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 20, 2010
    Inventors: Jin-bum Kim, Si-young Choi, Hyung-ik Lee, Ki-hong Kim, Yong-koo Kyoung
  • Patent number: 7718570
    Abstract: A method for manufacturing a carbon molecular sieve with increased microporosity; a method for manufacturing a carbon molecular sieve with increased microporosity and improved structural regularity; a carbon molecular sieve with increased microporosity; a carbon molecular sieve with increased microporosity and improved structural regularity; a catalyst for a fuel cell using the carbon molecular sieve; and a fuel cell using the catalyst are provided.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: May 18, 2010
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Chan-ho Pak, Ji-man Kim, Hyung-ik Lee
  • Publication number: 20100108972
    Abstract: A non-volatile semiconductor memory device includes a lower electrode, an upper electrode, a resistive layer pattern between the lower electrode and the upper electrode, and a filament seed embedded in the resistive layer pattern. The filament seed includes at least one of a carbon nanotube, a nanowire and a nanoparticle.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 6, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinshi Zhao, Hyung-Ik Lee, Seong-Ho Moon, In-Gyu Baek, Hyun-Jun Sim, Eun-Kyung Yim
  • Patent number: 7670582
    Abstract: Provided are a mesoporous carbon and a method of preparing the same, where the mesoporous carbon is prepared using phenanthrene as a carbon source and a mesoporous silica as a template. The mesoporous carbon has a significantly low plane resistance, which can be obtained without sacrificing other physical properties, and thus obtains a high conductivity and effectively transfers electrical energy. Accordingly, a fuel cell electrode or a fuel cell which is produced using the mesoporous carbon as a conductive material has high efficiency. Furthermore, the mesoporous carbon may be used in various electrochemical devices as a conductive material.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: March 2, 2010
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Chan-ho Pak, Sang-hoon Joo, Hyuk Chang, Ji-man Kim, Hyung-ik Lee
  • Publication number: 20090317663
    Abstract: Provided is a magnetic recording medium. The magnetic recording medium includes a substrate, a recording layer disposed on the substrate for magnetic recording, and a carbon protection layer, which includes a carbon layer and a blocking layer disposed in the carbon layer to block infiltration of external impurities, disposed on the recording layer. Since the blocking layer is disposed in the carbon layer, a thickness of the carbon protection layer can be reduced while a sufficient hardness to protect the recording layer can be ensured, and moreover, a softness of the surface of the carbon protection layer can be improved.
    Type: Application
    Filed: June 16, 2009
    Publication date: December 24, 2009
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Sok-hyun KONG, Hyung-ik LEE, Hoo-san LEE, Young-su CHUNG, Seong-yong YOON