Abstract: The present technology may include a voltage generation circuit configured to generate a plurality of voltages in response to at least one voltage control signal, and control logic configured to generate the at least one voltage control signal in order to adjust at least one of an under drive time and an under drive offset during an under drive operation of a semiconductor apparatus according to a temperature information signal and a pre-stored temperature characteristic signal of the semiconductor apparatus.

Abstract: A page buffer circuit including a data latch circuit and a sensing latch circuit. The data latch circuit configured to store data corresponding to a normal operation. The sensing latch circuit configured to receive and store the data in the data latch circuit in an entering operation in accordance with a suspend operation. The sensing latch circuit configured to transmit the data stored in the sensing latch circuit to the data latch circuit in a sensing operation in accordance with the suspend operation. The sensing latch circuit configured to suspend data in a memory cell, and to output the suspend data from the memory cell.

Abstract: A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.

Abstract: A method of operating a semiconductor device includes: starting a program operation on selected memory cells among a plurality of memory cells in response to a program command; suspending the program operation in response to a program suspend command; and performing a pre-verify operation by using a modified verify voltage in response to a program resume command.

Abstract: A method of operating a semiconductor device includes performing a pre-sensing operation on selected memory cells; and performing a main sensing operation on the selected memory cells. The performing of the main sensing operation includes selectively precharging first sensing nodes of a plurality of page buffers respectively corresponding to the selected memory cells, based on a result of the pre-sensing operation.

Abstract: A memory device includes plural memory cells and control circuitry. Each of the memory cells is capable of storing multi-bit data corresponding to an erase state and plural program states. The control circuitry is configured to divide plural program loops, which are performed to store the multi-bit data in the plural memory cells, into plural program groups and apply different program pulses, which correspond to each of the plural program groups, to the plural memory cells.

Abstract: A memory device includes a memory cell array including memory cells; a row control circuit coupled to the memory cells through word lines and configured to apply, to a selected word line during read operations, respective read voltages having different levels; a page buffer circuit coupled to the memory cells through bit lines and configured to adjust, according to a sensing control signal during each of the read operations, an amount of current flowing through the bit lines to sense the adjusted amount; and a read control circuit configured to adjust, during a second read operation subsequent to a first read operation among the read operations, a voltage level of the sensing control signal when a voltage level of a second read voltage corresponding to the second read operation is different from a level of a first read voltage corresponding to the first read operation.

Abstract: A semiconductor device may include a memory cell array including a memory block including a plurality of memory strings connected between a plurality of bit lines and a common source line, a control circuit that generates a page buffer control signal, a voltage control signal, and a drive address signal, a page buffer group including a plurality of page buffers and configured to form each of the plurality of bit lines to a preset voltage level, and generate a threshold voltage variation result on the basis of a change in the voltage level of each of the plurality of bit lines, a voltage generation circuit that generates a threshold verification voltage and a pass voltage, and a line drive circuit that drives a plurality of select lines to a level of the threshold verification voltage, and drives a plurality of word lines to a level of the pass voltage, during the threshold voltage variation verification.

Abstract: A semiconductor apparatus includes a memory cell array and a control circuit. The control circuit is configured to perform a program operation on target cells within the memory cell array, the program operation including a plurality of loops. The control circuit may be configured to apply a bit line voltage having a predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and configured to apply the bit line voltage having a higher level than the predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops.

Abstract: A memory device includes a memory cell array including memory cells; a row control circuit coupled to the memory cells through word lines and configured to apply, to a selected word line during read operations, respective read voltages having different levels; a page buffer circuit coupled to the memory cells through bit lines and configured to adjust, according to a sensing control signal during each of the read operations, an amount of current flowing through the bit lines to sense the adjusted amount; and a read control circuit configured to adjust, during a second read operation subsequent to a first read operation among the read operations, a voltage level of the sensing control signal when a voltage level of a second read voltage corresponding to the second read operation is different from a level of a first read voltage corresponding to the first read operation.

Abstract: A method of operating a semiconductor device includes performing a pre-sensing operation on selected memory cells; and performing a main sensing operation on the selected memory cells. The performing of the main sensing operation includes selectively precharging first sensing nodes of a plurality of page buffers respectively corresponding to the selected memory cells, based on a result of the pre-sensing operation.

Abstract: A memory device including: a memory device may include: a memory cell array, and a controller configured to perform program loops each comprising a voltage application operation, a word line holding operation, and a verification operation until a program operation for selected memory cells is successful, during the word line holding operation, apply a holding pass voltage having a higher level than a ground voltage to each of first word lines having a program state and second word lines having an erase state, which belong to unselected word lines among a plurality of word lines, during the verification operation, apply a verification pass voltage having a higher level than the holding pass voltage to K word lines that belong to the first word lines and the second word lines, and apply the holding pass voltage to remaining word lines except the K word lines, among the second word lines.

Abstract: A semiconductor device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation on memory cells selected from among the plurality of memory cells. The control logic is configured to control the program operation of the peripheral circuit. The control logic is configured to control the peripheral circuit to precharge bit lines respectively coupled to the selected memory cells to different voltage levels during a verify operation included in the program operation.

Abstract: A memory device comprising: a memory cell array including a plurality of memory cell strings coupled between a plurality of bit lines and a common source line, and a plurality of word lines coupled to the memory cell strings, and a control circuit configured to: repeat a program loop including a program pulse application operation and a verification operation until a program operation is successfully performed on memory cells that are coupled to a selected word line, a selected cell string, and the plurality of bit lines, additionally perform a channel precharge operation together with the program pulse application operation and the verification operation starting from a selected program loop, and vary a level of a precharge voltage applied to the common source line in the channel precharge operation according to an operation temperature.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells coupled between a common source line and a bit line, a peripheral circuit configured to perform a plurality of program loops, each including a program voltage application operation of applying a program voltage to a selected memory cell and a verify operation of verifying a program state of the selected memory cell, and a control logic configured to control, at the program voltage application operation, the peripheral circuit to apply a precharge voltage to the common source line and change at least one of a magnitude of the precharge voltage and a time during which the precharge voltage is applied, depending on a magnitude of the program voltage.

Abstract: An operating method of a non-volatile memory device includes simultaneously performing a program operation on a plurality of selection transistors included in a plurality of cell strings each including a corresponding selection transistor of the selection transistors and a plurality of memory cells, each of the cell strings being coupled between a common source line and a corresponding bit line of a plurality of bit lines; sequentially performing verification operations on respective groups of the selection transistors, the groups being coupled to respective selection lines; and sequentially storing results of the verification operations into respective data latch circuits within each of a plurality of page buffers coupled to the bit lines.

Abstract: A memory device includes a control signal generation circuit configured to generate a control signal at a voltage level corresponding to a current temperature in each operation period, among a plurality of operation periods, of a program operation, and a bit line control circuit configured to charge a bit line in response to the control signal.

Abstract: A page buffer circuit of a memory device includes a sensing circuit configured to sense a voltage level of a sensing node changed according to a state of a bit line during a sensing operation. The page buffer circuit also includes a clamping circuit connected to the sensing node, wherein the claiming circuit is configured to control the voltage level of the sensing node not to drop below a clamping level in a predetermined period of the sensing operation.

Abstract: A memory device includes strings and a peripheral circuit. The strings are connected between a bit line and a source line. The peripheral circuit is configured to perform an erase operation on a first string among the strings by applying an erase voltage to at least one of the bit line and the source line and configured to control a second string among the strings to be prohibited from being erased during the erase operation.

Abstract: A semiconductor memory device includes a memory cell array circuit and a driving force adjustment circuit. The memory cell array circuit includes a plurality of memory cells. The driving force adjustment circuit adjusts driving forces of a plurality of respective verify pass voltages based on whether or not the plurality of memory cells are programmed.