Patents by Inventor Hyung-jin Choi

Hyung-jin Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915762
    Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: February 27, 2024
    Assignee: SK hynix Inc.
    Inventors: Tae Hun Park, Dong Hun Kwak, Hyung Jin Choi
  • Patent number: 11901022
    Abstract: A nonvolatile memory device includes: a peripheral circuit for repeatedly performing program loops each including a program operation including a setup operation on the plurality of bit lines and an application operation of applying a program pulse to a selected word line and the verification operation, and a control logic circuit for controlling the peripheral circuit, wherein the peripheral circuit performs a first program loop of the program loops by: applying each a first and a second program pulses in each a first and a second section of the application operation, setting a first bit line to a first level and a second bit line to a second level lower than the first level from a start of the setup operation until an end of the first section, and resetting the first and the second bit line to the second level in the second section.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: February 13, 2024
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11894076
    Abstract: An operating method of a non-volatile memory device comprises: performing a foggy operation applying a first application voltage to a word line and applying a first verification voltage having a same level as or a higher level than a target threshold voltage to the word line, determining whether the foggy operation is completely performed according to whether a number of memory cells each having a threshold voltage higher than the first verification voltage is equal to or greater than a first number, performing a fine operation applying a second application voltage to the word line and applying a second verification voltage having the same level as the target threshold voltage, and determining whether the fine operation is completely performed, according to whether a number of memory cells each having a threshold voltage lower than the second verification voltage is less than or equal to a second number.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11887669
    Abstract: A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells capable of storing data. The control circuit performs a program operation for programming data in the plural non-volatile memory cells through a plurality of program loops, each program loop including a unit program operation for applying a program pulse to the plural non-volatile memory cells and a verification operation for verifying a result of the unit program operation. The control circuit uses a current detection circuit for detecting whether a threshold voltage distribution of the plural non-volatile memory cells satisfies a reference in a specific program loop of the plurality of program loops. The control circuit terminates the program operation after applying a preset program pulse to the plural non-volatile memory cells in a next program loop following the specific program loop.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: January 30, 2024
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Publication number: 20240028216
    Abstract: A memory device includes plural memory cells and control circuitry. Each of the memory cells is capable of storing multi-bit data corresponding to an erase state and plural program states. The control circuitry is configured to divide plural program loops, which are performed to store the multi-bit data in the plural memory cells, into plural program groups and apply different program pulses, which correspond to each of the plural program groups, to the plural memory cells.
    Type: Application
    Filed: November 18, 2022
    Publication date: January 25, 2024
    Inventor: Hyung Jin CHOI
  • Patent number: 11882703
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: January 23, 2024
    Assignee: SK hynix Inc.
    Inventors: Sungmook Lim, Dae Hwan Yun, Gil Bok Choi, Jae Hyeon Shin, In Gon Yang, Hyung Jin Choi
  • Patent number: 11875050
    Abstract: Provided herein is a memory device including a memory block with memory cells to which word lines and bit lines are connected; page buffers, connected to the memory block through the bit lines, during a program operation, configured to convert original data that is received from an external device into variable data that is divided into groups according to a number of specific data, and configured to apply a program enable voltage or a program inhibit voltage to the bit lines according to the variable data; and a data pattern manager configured to control the page buffers to convert the original data into the variable data during the program operation.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: January 16, 2024
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Publication number: 20230409214
    Abstract: A semiconductor device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a program operation on memory cells selected from among the plurality of memory cells. The control logic is configured to control the program operation of the peripheral circuit. The control logic is configured to control the peripheral circuit to precharge bit lines respectively coupled to the selected memory cells to different voltage levels during a verify operation included in the program operation.
    Type: Application
    Filed: November 2, 2022
    Publication date: December 21, 2023
    Applicant: SK hynix Inc.
    Inventors: Hyung Jin CHOI, Chan Sik PARK
  • Publication number: 20230410924
    Abstract: The present technology may include a voltage generation circuit configured to generate a plurality of voltages in response to at least one voltage control signal, and control logic configured to generate the at least one voltage control signal in order to adjust at least one of an under drive time and an under drive offset during an under drive operation of a semiconductor apparatus according to a temperature information signal and a pre-stored temperature characteristic signal of the semiconductor apparatus.
    Type: Application
    Filed: November 8, 2022
    Publication date: December 21, 2023
    Applicant: SK hynix Inc.
    Inventors: Hyung Jin CHOI, Gwi Han KO, Chan Hui JEONG
  • Publication number: 20230402104
    Abstract: A page buffer circuit including a data latch circuit and a sensing latch circuit. The data latch circuit configured to store data corresponding to a normal operation. The sensing latch circuit configured to receive and store the data in the data latch circuit in an entering operation in accordance with a suspend operation. The sensing latch circuit configured to transmit the data stored in the sensing latch circuit to the data latch circuit in a sensing operation in accordance with the suspend operation. The sensing latch circuit configured to suspend data in a memory cell, and to output the suspend data from the memory cell.
    Type: Application
    Filed: December 1, 2022
    Publication date: December 14, 2023
    Applicant: SK hynix Inc.
    Inventor: Hyung Jin CHOI
  • Publication number: 20230400986
    Abstract: A semiconductor apparatus includes a memory cell array and a control circuit. The control circuit is configured to perform a program operation on target cells within the memory cell array, the program operation including a plurality of loops. The control circuit may be configured to apply a bit line voltage having a predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and configured to apply the bit line voltage having a higher level than the predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops.
    Type: Application
    Filed: November 8, 2022
    Publication date: December 14, 2023
    Applicant: SK hynix Inc.
    Inventors: Hyung Jin CHOI, Gwi Han KO, Chan Hui JEONG
  • Patent number: 11842773
    Abstract: Provided herein is a page buffer, a semiconductor memory device with the page buffer, and a method of operating the semiconductor memory device. The page buffer includes a plurality of data latch components coupled to a sensing node, a bit line controller coupled between a bit line and the sensing node, the bit line controller configured to control a node value of the sensing node based on a program state of a memory cell that is coupled to the bit line during a program verify operation, and a sub-latch component configured to latch verification data based on the node value during the program verify operation, wherein each data latch component sets the node value to a first logic value when a program state that corresponds to program data has a threshold voltage distribution that is higher than that in a target program state during the program verify operation.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: December 12, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Publication number: 20230393759
    Abstract: A memory device, and a method of operating the same, includes a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, a weak word line information storage configured to store information about a weak word line among the plurality of word lines, and a program operation controller configured to control the peripheral circuit such that the program operation is performed in a first program mode or a second program mode depending on a result of determining whether a selected word line corresponding to an address provided from a memory controller is a weak word line by comparing word lines based on the information about the weak word line.
    Type: Application
    Filed: October 18, 2022
    Publication date: December 7, 2023
    Applicant: SK hynix Inc.
    Inventors: Chan Hui JEONG, Hyung Jin CHOI, Se Chun PARK
  • Patent number: 11776630
    Abstract: A memory device comprises a memory cell array and a control circuit. The control circuit applies a pass voltage to each of a selected and unselected word line from a first to second time point whenever a program loop is performed once. Then, the control circuit applies a program voltage to the selected word line and the pass voltage to the unselected word line from the second to third time point, performs a bit line precharge operation from a fourth time point ahead of the first time point to the second time point when a first program loop is performed, and performs the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, when the other program loops are performed.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: October 3, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Publication number: 20230290420
    Abstract: A semiconductor memory apparatus includes: a page buffer circuit, a pass/fail determination circuit, and an operation control circuit. The page buffer circuit may include a sensing latch circuit and a data latch circuit. The pass/fail determination circuit determines a pass/fail for a memory cell. The operation control circuit controls a program operation and a program verify operation to be performed on the memory cell.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 14, 2023
    Applicant: SK hynix Inc.
    Inventor: Hyung Jin CHOI
  • Publication number: 20230290412
    Abstract: A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array through word lines and bit lines, and suitable for performing one or more program loops on memory cells that are coupled to a selected word line of the word lines, each program loop including a program voltage application operation and a program verification operation; and a program control circuit suitable for controlling the peripheral circuit to decrease a level of a precharge voltage that is applied to the bit lines during the program verification operation when the number of program loops that are performed is greater than a reference number.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 14, 2023
    Applicant: SK hynix Inc.
    Inventor: Hyung Jin CHOI
  • Patent number: 11742035
    Abstract: A memory device may include a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to perform a program verify operation for a target program state among a plurality of program states on selected memory cells among the plurality of memory cells. The control logic is configured to control the peripheral circuit to precharge bit lines coupled to first memory cells among the selected memory cells and bit lines coupled to second memory cells among the selected memory cells in the program verify operation. The first memory cells are program-passed memory cells among memory cells programmed to a program state higher than the target program state among the plurality of program states. The second memory cells are memory cells programmed to a program state lower than or equal to the target program state among the plurality of program states.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: August 29, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Publication number: 20230229344
    Abstract: A semiconductor memory device may include a memory cell array circuit and a word line driving circuit. The memory cell array circuit may be connected with a plurality of word lines to store data in a program operation. The word line driving circuit may drive a selected word line among the word lines using a program voltage in the program operation. The word line driving circuit may drive each of non-selected word lines adjacent to the selected word line using a step pass voltage including at least two step voltages.
    Type: Application
    Filed: October 20, 2022
    Publication date: July 20, 2023
    Inventor: Hyung Jin CHOI
  • Patent number: 11657885
    Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a control logic circuit configured to control the peripheral circuit so that the program operation is performed. The control logic circuit controls a peripheral circuit so that memory cells to be programmed to first to (N?1)-th program states are programmed in a double program method using a main verify voltage and a sub verify voltage less than the main verify voltage during a verify operation and memory cells to be programmed to the N-th program state are programmed in a normal program method using the main verify voltage during the verify operation, when the verify operation of the memory cells corresponding to the (N?1)-th program state has failed.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11657882
    Abstract: A memory device including a plurality of memory cells, a threshold voltage distribution measurement component configured to measure a threshold voltage distribution of a first read operation of sensing data from programmed memory cells among the plurality of memory cells, and a threshold voltage distribution of a second read operation of sensing the data from the programmed memory cells and outputting the data to an outside, a distribution shift compensation table generator configured to calculate a shift direction and a shift distance based on a result of comparing the threshold voltage distribution of the first read operation and the threshold voltage distribution of the second read operation, and generate a distribution shift compensation table based on the shift direction and the shift distance, and a read operation controller configured to perform a third read operation on target memory cells based on the distribution shift compensation table.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi