Patents by Inventor Hyung Jin Lim

Hyung Jin Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128251
    Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Applicant: Samsung Display Co., LTD.
    Inventors: Kyung Jin JEON, So Young KOO, Eok Su KIM, Hyung Jun KIM, Yun Yong NAM, Jun Hyung LIM
  • Publication number: 20240127056
    Abstract: A training system includes a dynamic random access memory (DRAM) configured to buffer training data; a central processing unit (CPU) coupled to the DRAM and configured to downsample the training data and provide the DRAM with the downsampled training data; a computational storage consisting of a solid-state drive (SSD) and field-programmable gate array (FPGA) and configured to perform dimensionality reduction on the downsampled training data to generate training data batches; and a graphic processing unit (GPU) configured to perform training on the training data batches.
    Type: Application
    Filed: August 28, 2023
    Publication date: April 18, 2024
    Inventors: Jongryool KIM, Hyung Jin LIM, Kevin TANG, Shiju LI
  • Publication number: 20240108664
    Abstract: The present invention relates to a tumor-targeting Salmonella gallinarum strain and the use thereof. The tumor-targeting Salmonella gallinarum strain has excellent tumor proliferation inhibitory activity and enables tumor-specific targeting, and thus can be utilized for treatment and imaging of tumors without any side effects.
    Type: Application
    Filed: October 29, 2020
    Publication date: April 4, 2024
    Inventors: Hyon El CHOY, Jae Ho JEONG, Dae Jin LIM, Hyung Ju LIM, Kwangsoo KIM
  • Patent number: 11942482
    Abstract: A display device according to an embodiment includes a light blocking layer disposed on a substrate; an oxygen supply layer disposed on and contacting the light blocking layer; a semiconductor layer disposed on the oxygen supply layer; and a light emitting diode electrically connected with the semiconductor layer. The semiconductor layer includes an oxide semiconductor, and the oxygen supply layer includes a metal oxide that includes at least one of indium, zinc, gallium, and tin.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyung Jun Kim, So Young Koo, Eok Su Kim, Yun Yong Nam, Jun Hyung Lim, Kyung Jin Jeon
  • Patent number: 11942488
    Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: March 26, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung Jin Jeon, So Young Koo, Eok Su Kim, Hyung Jun Kim, Joon Seok Park, Jun Hyung Lim
  • Patent number: 11930858
    Abstract: An aerosol generating device according to an aspect comprises a main body that comprises a battery and a controller, a cartridge which is coupled to the main body and comprises a liquid storage that contains liquid composition and an atomization portion that generates an aerosol by heating the liquid composition contained in the liquid storage, and a cover that forms an inner space by being coupled to the main body such that the cartridge is arranged in the inner space, wherein the main body further comprises a light source that emits light toward an inside of the liquid storage, and the cover comprises a window hole through which light entitled from the light source toward the inside of the liquid storage is transmitted to the outside of the cover.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: March 19, 2024
    Assignee: KT&G CORPORATION
    Inventors: Hun Il Lim, Tae Hun Kim, Hyung Jin Jung, Jae Sung Choi, Jung Ho Han
  • Publication number: 20240065811
    Abstract: A dental implant in which an external thread structure of the implant and an internal polygonal part structure are improved, thereby being capable of preventing a fatigue fracture caused by stress concentration at a portion adjacent to the polygonal part inside the implant. The dental implant implantable into an alveolar bone tissue and forming an artificial tooth root includes an external bottom thread section machined up to a predetermined section upward from a bottom of an outer peripheral surface of the implant so that threads having large heights are formed by a first bit, and includes an external top thread section machined above the external bottom thread section so that threads having small heights are formed by a second bit having a different machining surface shape and a different width. The threads of each thread section have the same pitches and the same crest widths.
    Type: Application
    Filed: December 10, 2021
    Publication date: February 29, 2024
    Applicant: OSSTEMIMPLANT CO., LTD.
    Inventors: Soo Eon KIM, In Ho KIM, Hyung Jin LIM
  • Patent number: 11763041
    Abstract: A data storage device includes a nonvolatile memory device, a volatile memory device, a data encryption circuit configured to encrypt data outputted from the nonvolatile memory device, a data decryption circuit configured to decrypt encrypted data output from the data encryption circuit and configured to provide the decrypted data to the volatile memory device, and a processor configured to perform a first process that controls installation of a first in-storage program in the data storage device, a second process configured to manage a mapping table storing a relation between a logical address and a physical address of the nonvolatile memory device, and a third process configured to execute the first in-storage program.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: September 19, 2023
    Assignees: SK hynix Inc., The Board of Trustees of the University of Illinois
    Inventors: Jian Huang, Xiaohao Wang, Luyi Kang, Jong Ryool Kim, Hyung Jin Lim, Myeong Joon Kang, Chang Hwan Youn
  • Patent number: 11656979
    Abstract: A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memory access address; classify each memory access address into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and allocate the first memory for frequently accessed data associated with the frequently accessed address and the second memory for normal data associated with the normal accessed address.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventors: Miseon Han, Hyung Jin Lim, Jongryool Kim, Myeong Joon Kang
  • Patent number: 11494891
    Abstract: Disclosed are a method of inspecting and evaluating a coating state of a steel structure, and a system therefor. A plurality of vision images and thermal images are acquired. While acquiring the thermal images, a desired region is heated. After the thermal images and the vision images in a dynamic state are reconstructed into a time-spatial-integrated thermal image and a time-spatial-integrated vision image in a static state, respectively, an overlay image is generated by overlaying the two images. A deterioration region of a coating is detected, and coating deterioration is classified by characteristics. A size of the coating deterioration region is quantified. A thickness of the coating is inspected by analyzing thermal energy measured from the time-spatial-integrated thermal image. A coating grade is calculated by comprehensively evaluating a coating deterioration inspection result and a coating thickness inspection result. A state evaluation report for the steel structure is automatically created.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 8, 2022
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Hoon Sohn, Soonkyu Hwang, Hyeonjin Kim, Hyung Jin Lim
  • Publication number: 20220350932
    Abstract: A data storage device includes a nonvolatile memory device, a volatile memory device, a data encryption circuit configured to encrypt data outputted from the nonvolatile memory device, a data decryption circuit configured to decrypt encrypted data output from the data encryption circuit and configured to provide the decrypted data to the volatile memory device, and a processor configured to perform a first process that controls installation of a first in-storage program in the data storage device, a second process configured to manage a mapping table storing a relation between a logical address and a physical address of the nonvolatile memory device, and a third process configured to execute the first in-storage program.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Inventors: Jian HUANG, Xiaohao WANG, Luyi KANG, Jong Ryool KIM, Hyung Jin LIM, Myeong Joon KANG, Chang Hwan YOUN
  • Patent number: 11422737
    Abstract: A method for operating a controller configured to control subsystems in a network, each subsystem including a plurality of memory regions, includes testing a compressibility ratio of data and selecting, according to the compressibility ratio, memory regions for storing the data and replicated data.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventors: Jun Hee Ryu, Kwang Jin Ko, Hyung Jin Lim
  • Publication number: 20220229552
    Abstract: A computer system includes a first main memory, a second main memory having an access latency different from that of the first main memory and, a memory management system configured to manage the second main memory by dividing it into a plurality of pages, detect a hot page, among the plurality of pages, based on a write count of data stored in the second main memory, and move data of the hot page to a new page in the second main memory and to the first main memory.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: Mi Seon HAN, Hyung Jin LIM, Jong Ryool KIM, Myeong Joon KANG
  • Publication number: 20220197787
    Abstract: A heterogeneous memory system includes a memory device including first and second memories and a controller including a cache. The controller identifies memory access addresses among addresses for memory regions of the memory device; track, for a set period, a number of memory accesses for each memory access address; classify each memory access address into a frequently accessed address or a normal accessed address based on the number of memory accesses in the set period; and allocate the first memory for frequently accessed data associated with the frequently accessed address and the second memory for normal data associated with the normal accessed address.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 23, 2022
    Inventors: Miseon Han, Hyung Jin Lim, Jongryool Kim, Myeong Joon Kang
  • Patent number: 11360697
    Abstract: A memory system includes a non-volatile memory device and a controller. The non-volatile memory device includes plural memory groups storing plural chunks. The controller is capable of generating the plural chunks including data chunks and parity chunks based on original data, assign different priorities to the data chunks and the parity chunks, and recovering at least one chunk among the plural chunks based on the different priorities when an operation regarding the at least one chunk fails.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Jun Hee Ryu, Kwang Jin Ko, Hyung Jin Lim
  • Patent number: 11354188
    Abstract: A host handles reliability management of memory systems. The host analyzes characteristics of data associated with a select memory system among the memory systems. The host determines a reliability control mode and one or more reliability schemes among reliability schemes to be applied to the select memory system based on the characteristics. The host provides reliability management information indicating the reliability control mode to the select memory system. The plurality of reliability schemes includes error correction code (ECC), read retry, intra redundancy and refresh schemes.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Jongryool Kim, Hyung Jin Lim, Miseon Han, Myeong Joon Kang, Suchang Kim, Pui York Wong
  • Publication number: 20220171564
    Abstract: A memory system includes a memory device including a first memory block and a second memory block, wherein the first memory block stores a first data chunk having a first size and the second memory block stores a second data chunk having a second size, and the first size is less than the second size; and a controller operatively coupled to the memory device, wherein the controller is configured to read the second data chunk from the second memory block, correct at least one error of the second data chunk when the at least one error is detected, and copy a portion of the second data chunk to the first memory block, wherein the portion of the second data chunk is error-corrected and has the first size.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 2, 2022
    Inventors: Jun Hee RYU, Hyung Jin LIM, Myeong Joon KANG, Kwang Jin KO, Woo Suk CHUNG, Yong JIN
  • Publication number: 20220091931
    Abstract: A host handles reliability management of memory systems. The host analyzes characteristics of data associated with a select memory system among the memory systems. The host determines a reliability control mode and one or more reliability schemes among reliability schemes to be applied to the select memory system based on the characteristics. The host provides reliability management information indicating the reliability control mode to the select memory system. The plurality of reliability schemes includes error correction code (ECC), read retry, intra redundancy and refresh schemes.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Jongryool KIM, Hyung Jin LIM, Miseon HAN, Myeong Joon KANG, Suchang KIM, Pui York WONG
  • Publication number: 20210334034
    Abstract: A memory system includes a non-volatile memory device including plural memory groups storing plural chunks; and a controller configured to generate the plural chunks including data chunks and parity chunks based on original data, assign different priorities to the data chunks and the parity chunks, and recover at least one chunk among the plurality of chunks based on the different priorities when an operation regarding the at least one chunk fails.
    Type: Application
    Filed: November 10, 2020
    Publication date: October 28, 2021
    Inventors: Jun Hee RYU, Kwang Jin KO, Hyung Jin LIM
  • Publication number: 20210311656
    Abstract: A method for operating a controller configured to control subsystems in a network, each subsystem including a plurality of memory regions, includes testing a compressibility ratio of data and selecting, according to the compressibility ratio, memory regions for storing the data and replicated data.
    Type: Application
    Filed: September 17, 2020
    Publication date: October 7, 2021
    Inventors: Jun Hee RYU, Kwang Jin KO, Hyung Jin LIM