Abstract: A method for fabricating a mask for manufacturing a semiconductor device is provided. The method includes generating a first target pattern including a step portion having an inner corner and an outer corner that are spaced apart in a vertical direction; generating a second target pattern from the first target pattern; performing optical proximity correction on the second target pattern to generate a final pattern; and fabricating the mask using the final pattern. Generating the second target pattern includes forming a recess extending inwardly and in a diagonal direction relative to the inner corner of the step portion; and forming a protrusion protruding outwardly and in the diagonal direction relative to the outer corner of the step portion.

Abstract: A method for fabricating mask is provided. The method includes generating a second target pattern from a first target pattern, where the first target pattern includes first straight edges, and the second target pattern includes second straight edges and curved edges. Optical proximity correction is performed on the second target pattern to generating a mask pattern. The mask is fabricated using the mask pattern. Generating the second target pattern includes changing corner portions of the first target pattern into a curve to generate the curved edges.

Abstract: Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.

Abstract: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

Abstract: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

Abstract: Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.

Abstract: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

Abstract: There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.