Abstract: A Galois field processor having a dual parallel data path for a Bose Chaudhuri Hocquenghem/Reed-Solomon (BCH/RS) decoder is provided. The Galois field processor includes a syndrome register block for storing syndrome values transmitted by a syndrome generating block, a correction polynomial register block, a connection polynomial register block, and a discrepancy register block. A dual mode Galois field data path (DMGFDP) includes a first data path for receiving the respective outputs of the syndrome register block, the correction polynomial register block, the connection polynomial register block, and the discrepancy register block, performing predetermined operations related to the even-degree coefficients of correction and connection polynomial, and outputting the even-degree coefficient output. A second data path performs predetermined operations related to the odd-degree coefficients of the correction and connection polynomial and outputs the odd-degree coefficient output.

Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

Abstract: An apparatus and method for buffering NRZ data patterns in order to generate a recording pulse in a CD-RW/DVD-RW system are provided.

Abstract: A method and apparatus for dividing a long polynomial expression in a finite field. Elements in a dividend polynomial are grouped into a plurality of groups and combined according to a superposition of the finite field. Then, a group-based parallel processing operation is performed with respect to the combined results on the basis of a lookahead technique and a partial-division process to sequentially remove the groups up to the last one for inter-symbol division in the finite field. A first group storage block stores the first one of the groups and an intermediate group storage block adds partial-remainders from the previous and current groups to form a new intermediate group. A remainder generation block adds partial-remainders from the previous and last groups to generate the overall remainder. A partial-quotient generation block generates partial-quotients in response to output data from the first group storage block and intermediate group storage block.

Abstract: A memory device employs multiple dual-bank RAMs to allow simultaneous write/read operations. The memory may be utilized in a high-speed block pipelined Reed-Solomon decoder for temporarily storing input codewords during pipelined processing. A memory controller enables writing to and reading from the dual-bank RAMs during each of successive frame periods such that each bank of the dual-bank RAMs is read every given number of frame periods and is written every same given number of frame periods, and such that a read bank is contained in a different one of the dual-bank RAMs than is a write bank in each of the successive frame periods.

Abstract: A method and system for error correcting C1/PI words using error locations detected by EFM/EFM+ decoder are provided. The method for channel decoding and error correcting includes: (a) setting up a channel code; (b) producing demodulated data including information data symbols and erasure flags by modulating channel data symbols, using the channel code; and (c) performing an error-erasure correction on the information data symbols of the demodulated data, using error locations indicated by the erasure flags. The system for channel decoding and error correcting includes a channel decoder with a channel code for producing the demodulated data having the information data symbols and the erasure flags by demodulating the channel data symbols, a memory for storing the demodulated data, and a decoding unit for performing an error-erasure correction on the information data symbols, using the error locations indicated by the erasure flags having a predetermined value.