Patents by Inventor Hyung Joun Yoo

Hyung Joun Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190180931
    Abstract: Disclosed are an inductor layout and an integrated circuit device with improved isolation between inductors through shielding magnetic coupling between the inductors. first and second inductor coils are horizontally spaced apart from each other. A conductor loop is disposed in parallel above the first inductor coil and shields magnetic coupling between the first and second inductor coils in the manner that a part of magnetic flux of a first time-varying magnetic field generated by the second inductor coil is cancelled by magnetic flux of a second magnetic field generated by an induction current that flows in the conductor loop magnetically interlinked with the first time-varying magnetic field. The inductor layout can be applied to an RFIC device to reduce magnetic coupling between inductors of a power amplifier and an oscillator. Improved performance of the device and a very small RFIC can be achieved.
    Type: Application
    Filed: February 23, 2017
    Publication date: June 13, 2019
    Applicants: Korea Advanced Institute of Science and Technology, Research & Business Foundation Sungkyunkwan University
    Inventors: Hyung-joun Yoo, Sang-sun Yoo, Kang-yoon Lee
  • Publication number: 20130321030
    Abstract: The present invention relates to a movement average filter based on charge sampling and a moving average filtering method using the same. The moving average filter includes a voltage-current converter and a first sampling unit. The voltage-current converter converts an input voltage signal into an input current signal and outputs the input current signal. The first sampling unit includes a first 1-unit sampler, an ?-unit sampler, and a second 1-unit sampler connected in parallel between an output terminal of the voltage-current converter and a filtered signal output terminal, wherein each of the first 1-unit sampler, the ?-unit sampler, and the second 1-unit sampler has a sampling capacitor bank for performing charge sampling. A ratio of sampling capacitances of sampling capacitor banks of the first 1-unit sampler, the ?-unit sampler, and the second 1-unit sampler is 1:?:1, wherein a is adjusted to have a value between 1 and 2.
    Type: Application
    Filed: November 13, 2012
    Publication date: December 5, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jang-Hyun Park, Seong-Hoon Choi, In-Su Jang, Chang-Beom Kim, Yong-Ho Cho, Soo-Hwan Shin, Soon-Jae Kweon, Hyung-Joun Yoo
  • Patent number: 6292084
    Abstract: A fine inductor having a 3-dimensional coil structure is disclosed. The inductor includes an insulating layer having a groove, a plurality of first conductive patterns wherein the respective first conductive patterns cover bottom and both walls of the groove formed in the insulating layer, both ends of the respective first conductive patterns are extended over upper surface of both sides of the groove, and each of the first conductive patterns is disposed at a predetermined space between adjacent first conductive patterns, and a plurality of second conductive patterns wherein one ends of the respective second conductive patterns are connected to the one ends of the first conductive patterns extended over upper surface and the other ends of the respective second conductive patterns are connected to the other ends of the adjacent first conductive patterns extended over upper surface, thereby forming a coil structure together with the first conductive patterns.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: September 18, 2001
    Assignee: Electronics and Telecommunication Research Institute
    Inventors: Chang Auck Choi, Jong Hyun Lee, Won Ick Jang, Yong Il Lee, Jong Tae Baek, Hyung Joun Yoo
  • Patent number: 6137219
    Abstract: A field emission display having an n-channel high voltage thin film transistor is disclosed. According to the present invention, a signal for driving pixels controls by the nHVTFT attached with each pixel, therefore, the signal voltage of row and column drivers is exceedingly decreased. As a result, it is possible to implement a field emission display capable of providing a high quality picture in a low consumption power, a low driving voltage and inexpensive to manufacture, and preventing a line cross talk using the nHVTFT. By using a cylindrical resistive body underlying a cone-shaped emitter tip, the present invention is to provide a field emission display having an excellent contollability and stability of the emission current, and a dynamic driving capability.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: October 24, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yoon Ho Song, Jin Ho Lee, Seung Youl Kang, Kyoung Ik Cho, Hyung Joun Yoo
  • Patent number: 6101047
    Abstract: Provided with an optical system which is applicable to an exposure apparatus used in the manufacture of semiconductors and includes a combination of a spherical mirror having a function of refraction and lenses for astigmation control, using a CaF.sub.2 lens as the last lens, thereby making it possible to use a light source operating at a short wavelength and a wide bandwidth, enhance the life of the optical system, and transfer the enlarge pattern of a mask onto the wafer for realizing fine line width.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: August 8, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hai Bin Chung, Jong Soo Kim, Kag Hyeon Lee, Doh Hoon Kim, Sang Soo Choi, Hyung Joun Yoo
  • Patent number: 5953580
    Abstract: A method of manufacturing a vacuum device utilizing a sputtering process is disclosed. According to the present invention, the vacuum device includes a silicon substrate. An emission electrode having a sharp ended tip is formed by etching the silicon substrate. An insulating layer is formed on the silicon substrate so as to make the entire structure of the emission electrode to be exposed, with the emission electrode being surrounded by the insulating layer. A gate electrode is then formed adjacent to the sharp ended tip of the emission electrode. According to the present invention, it has advantages that the emission electrode is manufactured by forming the silicon pillar using the isotropic etching and anisotropic etching and the gate electrode can be easily formed adjacent to the emission electrode by using the sputtering method after the gate insulating layer is formed.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: September 14, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Weon Kang, Jin Ho Lee, Kyoung Ik Cho, Hyung Joun Yoo
  • Patent number: 5939833
    Abstract: The present invention relates to a field emission display which applies a field emission device (or field emitter) to a flat panel display. The field emission display in accordance with the present invention has the lower plate in which the pixel array and the scan and data driving circuits are integrated one insulating substrate, therefore, it is possible to implement a field emission display capable of providing a high quality picture in a low price. The voltage is applied to the scan and data driving circuits may considerably decrease through the tin film transistor attached to each pixel. The field emission characteristics are stabilized by the resistor attached to the field emission device so that reliable field emission display may be fabricated. Further, since all the processes are carried out at a low temperature, a glass, which is low in price and has a large area, may be used as an insulating substrate.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: August 17, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yoon-Ho Song, Jin-Ho Lee, Kyoung-Ik Cho, Hyung-Joun Yoo
  • Patent number: 5878105
    Abstract: An X-ray mask, which is used in transferring an image formed on a patterned mask to a wafer by exposing the mask with an X-ray, comprises a supplementary substrate attached to the back side of a support ring for preventing a thermal distortion of the X-ray mask due to the difference of thermal coefficient of expansion between a mask substrate and the support ring and for improving the resistance to the external mechanical stress, the supplementary substrate being made of the same material as the mask substrate and obtained through the same processing steps as the mask substrate.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: March 2, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Jin Jeon, Jin Man Jung, Sang Soo Choi, Bo Woo Kim, Hyung Joun Yoo
  • Patent number: 5843837
    Abstract: A contact hole burying method is provided including the steps of: coating an oxide layer on a substrate and removing the oxide layer except for a portion thereof to form a contact hole extending through the oxide layer in electrical contact with the oxide layer; sequentially forming a metal barrier layer and wet layer on the oxide layer and inside the contact hole to form an electrical connection to the substrate; forming a conductive metal layer on the wet layer; removing impurity ions and oxide material, which remain in the conductive metal layer which decrease mobility of metal atoms on a surface of said conductive layer due to absorption and oxidation, by a cleaning-etching process using a plasma; and reflowing the conductive metal layer at a relatively low temperature in a reactive furnace where the cleaning-etching process is performed to completely fill the contact hole.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: December 1, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong-Tae Baek, Youn-Tae Kim, Hyung-Joun Yoo
  • Patent number: 5810935
    Abstract: An apparatus for transferring a wafer in a semiconductor manufacturing process, and for carrying a wafer between a cassette and a wafer chuck without an additional tool such as a tripod. The apparatus includes: a holder capable of holding the side of the wafer; a wafer transfer assembly including an actuator of the holder and a detector that detects a malfunction of the holder; and a process reactor having a vacuum exhaust port installed under a wafer chuck so as to guide gas in an axially-symmetric flow pattern. The holder grasps the rounded side of a wafer. Removal of additional tools makes the structure of an overall system more simple and an exhaust port can be installed under the reactor so as to cause processing gas to be guided in an axially-symmetric flow, resulting in an enhancement of the process uniformity.
    Type: Grant
    Filed: November 29, 1995
    Date of Patent: September 22, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong-Hyun Lee, Hyung-Joun Yoo, Boo-Yeon Choi, Won-Ick Jang, Ki-Ho Jang
  • Patent number: 5796804
    Abstract: A X-ray mask structure which reduces the distortion of the membrane, the X-ray mask structure including, a mask substrate having an opening in the central part thereof, a membrane formed on the mask substrate, the membrane having the chip site on which absorbers are arranged according to a desired pattern of a semiconductor device, and a support ring for supporting the mask substrate, which is defined by a plurality of fragments.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: August 18, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Jin Jeon, Sang Soo Choi, Hai Bin Chung, Jong Hyun Lee, Hyung Joun Yoo
  • Patent number: 5783749
    Abstract: A vibrating disk type micro-gyroscope and a method of manufacture thereof are disclosed. The micro-gyroscope includes a support platform for supporting a vibrating disk, the vibrating disk converting a resonance frequency into two beat frequencies, a bottom detection electrode for detecting the angular velocity of the gyroscope from a detection of the electrostatic capacitance changes between the bottom detection electrode and the vibrating disk, and an upper drive electrode for exciting the vibrating disk. The method includes the steps of: depositing an insulator layer, a polycrystalline silicon layer, the bottom detection layer, and the bottom sacrificial layer; dry etching the bottom sacrificial layer; depositing polycrystalline silicon doped with dopants; dry etching every area except the support platform and the vibrating disk; depositing an oxide upper sacrificial layer; and forming a pattern and then wet etching the upper sacrificial layer and the bottom sacrificial layer.
    Type: Grant
    Filed: July 5, 1996
    Date of Patent: July 21, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong-Hyun Lee, Boo-Yeon Choi, Kyung-Ho Park, Hyung-Joun Yoo
  • Patent number: 5677089
    Abstract: A photomask according to the present invention for forming a T-gate electrode for Metal Semiconductor Field Effect Transistor and High Electron Mobility Transistor by performing each of the exposing process and the developing process once is disclosed. The photomask is composed of a primary mask positioned at the top surface of the transparent substrate made of Silica glass and a secondary mask positioned at the top surface of the transparent substrate for enhancing the resolution of the primary mask. The primary mask includes an opaque layer in which a material for mask pattern of, for example, Cr or Fe.sub.2 O.sub.3, or other opaque materials is deposited at the bottom surface of the transparent substrate, thereby preventing the light radiated from being transmitted, and a first and second patterns for forming the leg portion and the head portion of the T-gate electrode by simultaneously radiating the light into the exposed portion of the transparent substrate.
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: October 14, 1997
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Byung-Sun Park, Yong-Ho Oh, Sang-Soo Choi, Hyung-Joun Yoo
  • Patent number: 5543253
    Abstract: The present invention relates to a photomask for forming a T-shaped gate structure on a high speed FET through a photolithography, comprising opaque layer patterns 2 and 2a for defining a head portion of the T-shaped gate structure and half-tone layer patterns 3 and 3a for defining a foot portion thereof.The half-tone film patterns composed of a chrome layer are deposited to a thickness thinner than that of the opaque layer patterns so that the half-tone layer patterns show a relatively lower transmittance to an incident beam.The application of the photomask of the invention to the process for forming a T-shaped gate structure improves process reproducibility and leads to great cost savings.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: August 6, 1996
    Assignee: Electronics & Telecommunications Research Inst.
    Inventors: Byung-Sun Park, Yong-Ho Oh, Sang-Soo Choi, Hyung-Joun Yoo