Abstract: A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. Each of the semiconductor chips includes a first chip enablement pad connected to the at least one first chip enablement finger, a second chip enablement pad connected to the at least one second chip enablement finger, and a chip enablement pad selection pad connected to the chip enablement pad selection finger. The first chip enablement pads of the semiconductor chips or the second chip enablement pads of the semiconductor chips are optionally activated by a signal applied to the chip enablement pad selection finger.

Abstract: A semiconductor package may be provided. A semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip and a second semiconductor chip which are disposed adjacent to each other over a first surface of the substrate. The semiconductor package may include first bonding wires which electrically couple the first semiconductor chip and the substrate. The semiconductor package may include an insulation adhesive which is interposed between the second semiconductor chip and the substrate. The first bonding wires may be disposed to pass through the insulation adhesive and electrically couple the first semiconductor chip and the substrate.

Abstract: A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. Each of the semiconductor chips includes a first chip enablement pad connected to the at least one first chip enablement finger, a second chip enablement pad connected to the at least one second chip enablement finger, and a chip enablement pad selection pad connected to the chip enablement pad selection finger. The first chip enablement pads of the semiconductor chips or the second chip enablement pads of the semiconductor chips are optionally activated by a signal applied to the chip enablement pad selection finger.

Abstract: A semiconductor package includes a substrate, a chip disposed over a top surface of the substrate, an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip, a ground pad disposed in the substrate to contact a bottom surface of the substrate, and a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad. A method of testing the semiconductor package is performed using a loop circuit to which a current is applied, the loop circuit being formed by electrically coupling the ground pad, the EMI shielding layer, and the test pad.

Abstract: A semiconductor package may be provided. A semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip and a second semiconductor chip which are disposed adjacent to each other over a first surface of the substrate. The semiconductor package may include first bonding wires which electrically couple the first semiconductor chip and the substrate. The semiconductor package may include an insulation adhesive which is interposed between the second semiconductor chip and the substrate. The first bonding wires may be disposed to pass through the insulation adhesive and electrically couple the first semiconductor chip and the substrate.

Abstract: A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.

Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package may include a package substrate and at least one chip disposed on a first surface of the package substrate. The semiconductor package may include a boundary wall attached to the package substrate to surround the chip. The semiconductor package may include at least one bonding wire coupling the boundary wall to the package substrate. The semiconductor package may include a conductive roof covering a top surface of the boundary wall and extended to cover the first surface of the package substrate and the at least one chip.

Abstract: A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.

Abstract: Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (EMI) shielding layer covering the molding member, the EMI shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. The plurality of first extended ground lines include end portions that are exposed at the sidewalls of the substrate.

Abstract: Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (EMI) shielding layer covering the molding member, the EMI shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. The plurality of first extended ground lines include end portions that are exposed at the sidewalls of the substrate.

Abstract: Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (EMI) shielding layer covering the molding member, the EMI shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. The plurality of first extended ground lines include end portions that are exposed at the sidewalls of the substrate.

Abstract: Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (EMI) shielding layer covering the molding member, the EMI shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. The plurality of first extended ground lines include end portions that are exposed at the sidewalls of the substrate.

Abstract: A semiconductor package includes a substrate, a chip disposed over a top surface of the substrate, an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip, a ground pad disposed in the substrate to contact a bottom surface of the substrate, and a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad. A method of testing the semiconductor package is performed using a loop circuit to which a current is applied, the loop circuit being formed by electrically coupling the ground pad, the EMI shielding layer, and the test pad.

Abstract: A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

Abstract: A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.