Abstract: A method for manufacturing a CMOS semiconductor device having twin wells is disclosed. The method of manufacturing the CMOS device comprises the following. A silicon substrate is provided. A thick oxide layer is deposited and a first photoresist layer is coated sequentially on the silicon substrate. Then an N-well mask pattern is formed by removing a portion of the first photoresist layer, thereby defining an alignment-key region and N-well region and forming a thin oxide layer on such regions. An N-type impurity implantion process is then performed through exposed portions of the thin oxide layer into the silicon substrate, and the first photoresist layer portions remaining on the thick oxide layer are removed, to thereby expose the entire surface of the thick oxide layer. A second photoresist layer is coated on the entire surface of the oxide layer.