Abstract: A battery management apparatus includes: a measuring unit to measure voltage and capacity of a battery cell; a profile generating unit to generate a battery profile representing a correspondence between the voltage and the capacity measured by the measuring unit and generate a positive electrode profile of the battery cell based on the generated battery profile and a reference negative electrode profile and a reference negative electrode differential profile preset for the battery cell; and a control unit configured to receive the generated positive electrode profile from the profile generating unit, derive a conversion function representing conversion information from the reference positive electrode profile to the generated positive electrode profile, generate a positive electrode prediction profile for the battery cell from the reference positive electrode profile based on the derived conversion function, and generate a battery prediction profile for the battery cell based on the generated positive electro

Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.

Abstract: A display device according to an embodiment includes: a first conductive layer that is disposed on a substrate; a transistor that is disposed on the substrate; and a light emitting element that is electrically connected to the transistor, wherein the transistor includes a semiconductor layer that at least partially overlaps the first conductive layer and is disposed on the first conductive layer, and a gate electrode that is disposed on the semiconductor layer. The semiconductor layer includes a first region that does not overlap the first conductive layer, a third region that overlaps the first conductive layer, and a second region that is disposed between the first region and the third region and traverses an edge of the first conductive layer. The first width of the semiconductor layer in the first region is smaller than a second width of the semiconductor layer in the second region.

Abstract: A display device includes: a substrate; a light blocking layer of a driving transistor and an active layer of a switching transistor on the substrate; a buffer layer on the light blocking layer, the buffer layer overlapping the light blocking layer; an active layer of the driving transistor on the buffer layer; a first gate insulating layer on the active layer of the driving transistor and the active layer of the switching transistor; and a first gate electrode on the first gate insulating layer and overlapping the active layer of the driving transistor and a second gate electrode overlapping the active layer of the switching transistor, wherein the light blocking layer and the active layer of the switching transistor are on a same layer.

Abstract: Provided is a display device including a voltage line, a passivation layer disposed on the voltage line and having an undercut shape, a first connecting electrode disposed inside the undercut shape, a second connecting electrode electrically connecting the voltage line and the first connecting line, and a common electrode electrically connected to the voltage line through at least one of the first connecting electrode and the second connecting electrode.

Abstract: A display device includes: a substrate; a first semiconductor layer disposed on the substrate, where the first semiconductor layer includes a channel region and a doped region; a first gate electrode disposed to overlap the channel region of the first semiconductor layer; an intermediate film disposed on the first semiconductor layer and the first gate electrode; and a first electrode disposed on the intermediate film, where an opening is defined through the intermediate film to overlap the doped region of the first semiconductor layer, the doped region of the first semiconductor layer and the first electrode contacts each other through the opening, and an area of a cross-section of the opening parallel to the substrate is in a range of about 49 ?m2 to about 81 ?m2.

Abstract: A display device includes: a substrate; a barrier layer on the substrate, and including: a trench area recessed in a direction towards the substrate; and a flat area surrounding the trench area, and having a flat upper surface; and a switching transistor and a driving transistor on the barrier layer. The switching transistor includes: a first active layer on the barrier layer, at least a portion of the first active layer being located at the trench area, the first active layer including a channel area, and a source area and a drain area at opposite sides of the channel area; a first gate electrode on the first active layer; and a first upper electrode and a second upper electrode on and connected to the first active layer.

Abstract: A multilayer electronic component, may include: a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween, the body having first and second surfaces opposing each other, third and fourth surfaces opposing each other, and fifth and sixth surfaces opposing each other, the first surface including first and second band electrodes disposed to be spaced apart from each other; a first external electrode disposed on the third surface and connected to the first internal electrode and the first band electrode; a second external electrode disposed on the fourth surface and connected to the second internal electrode and the second band electrode; a first plating layer disposed on the first external electrode and the first band electrode; and a second plating layer disposed on the second external electrode and the second band electrode.

Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.

Abstract: A display device includes a substrate and a pixel disposed on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor member and a first gate electrode. The first semiconductor member includes an oxide semiconductor material. The first gate electrode is disposed between the first semiconductor member and the substrate. The second transistor includes a second semiconductor member and a second gate electrode. The second semiconductor member includes the oxide semiconductor material. The second semiconductor member is disposed between the second gate electrode and the substrate. The third transistor includes a third semiconductor member including silicon.

Abstract: A multilayer electronic component includes: a body including dielectric layers and first and second internal electrodes and having first to sixth surfaces; a first external electrode including a first connection portion on the third surface, a first band portion on the first surface, and a third band portion on the second surface; a second external electrode including a second connection portion on the fourth surface, a second band portion on the first surface, and a fourth band portion on the second surface; a cover layer disposed on the first and second connecting portions and disposed to cover the second surface and the third and fourth band portions; a first plating layer disposed on the first band portion; and a second plating layer disposed on the second band portion. The cover layer includes a base layer, having hydrophilicity, and an insulating layer disposed on the base layer.

Abstract: A transistor includes a gate electrode, an active layer facing the gate electrode, and a source electrode and a drain electrode connected to the active layer. The active layer includes a lower active layer including an oxide-based semiconductor material, and an upper active layer including the oxide-based semiconductor material and an oxygen-gettering material.

Abstract: A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.

Abstract: A multilayer electronic component includes: a body including a dielectric layer and first and second internal electrodes and having first to sixth surfaces; a first external electrode including a first connection portion on the third surface, a first band portion on the first surface, and a third band portion on the second surface; a second external electrode including a second connection portion on the fourth surface, a second band portion on the first surface, and a fourth band portion on the second surface; an insulating layer disposed on the first and second connection portions and covering the second surface, and third and fourth band portions; and first and second plating layers respectively disposed on the first and second band portions. The insulating layer includes an oxide containing Ti. The dielectric layer includes one of BaTiO3, (Ba1-xCax) TiO3 (0<x<1) , Ba(Ti1-yCay)O3 (0<y<1) , (Ba1-xCax) (Ti1-yZry)O3 (0<x<1, 0<y<1) and Ba(Ti1-yZry)O3 (0<y<1) as a main component.

Abstract: A multilayer electronic component includes a body including a dielectric layer and a first internal electrode and a second internal electrode having first to sixth surfaces, a first external electrode including a first connection portion on the third surface, a first band portion on a portion of the first surface, and a third band portion on a portion of the second surface, a second external electrode including a second connection portion on the fourth surface, a second band portion on a portion of the first surface, and a fourth band portion on a portion of the second surface, an insulating layer disposed on the first and second connection portions and covering the second surface and the third and fourth band portions, a first plating layer disposed on the first band portion, and a second plating layer disposed on the second band portion. The insulating layer includes an oxide containing Ba.

Abstract: A multilayer electronic component includes a body including first and second surfaces opposing each other in a first direction, and third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction; a first external electrode including a first connection portion disposed on the third surface and a first band portion extending from the first connection portion to a first portion of the first surface; a second external electrode including a second connection portion disposed on the fourth surface and a second band portion extending from the second connection portion to a first portion of the first surface; an insulating layer disposed on the second surface and extending to the first and second connection portions, the insulating layer including a first glass and a first oxide including aluminum (Al).

Abstract: A multilayer electronic component includes a body having a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer interposed therebetween. The body has a hexahedral shape. A first external electrode includes a first connection portion disposed on a third surface, and first and third band portions extending from the first connection portion respectively onto a portion of a first and a second surface. A second external electrode includes a second connection portion disposed on a fourth surface, and second and fourth band portions extending from the second connection portion respectively onto a portion of the first and second surfaces. An insulating layer including an oxide containing hafnium is disposed on the first and second connection portions and covers the second surface and the third and fourth band portions. First and second plating layers are disposed respectively on the first and second band portions.

Abstract: A multilayer electronic component includes a body including first and second surfaces opposing each other in a first direction, and third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction; a first external electrode including a first connection portion disposed on the third surface, and a third band portion extending from the first connection portion to a portion of the second surface; a second external electrode including a second connection portion disposed on the fourth surface, and a fourth band portion extending from the second connection portion to a portion of the second surface; an insulating layer disposed on the first and second connection portions and covering the second surface and the third and fourth band portions; the insulating layer includes an oxide including zirconium (Zr).

Abstract: A multilayer electronic component includes: a body including a dielectric layer and first and second internal electrodes, and including first to sixth surfaces; a first external electrode including a first connection portion on the third surface, a first band portion extending from the first connection portion onto the first surface, and a third band portion extending from the first connection portion onto the second surface; a second external electrode including a second connection portion on the fourth surface, a second band portion extending from the second connection portion onto the first surface, and a fourth band portion extending from the second connection portion onto the second surface; an insulating layer including oxide including aluminum (Al), disposed on the first and second connection portions, and covering the second surface and the third and fourth band portions; and first and second plating layers respectively disposed on the first and second band portions.

Abstract: A battery management apparatus and method according to an embodiment of the present disclosure is directed to obtaining a positive electrode profile and a negative electrode profile for a battery cell in a non-destructive manner by appropriately adjusting a preset negative electrode profile. According to one aspect of the present disclosure, by using the battery profile and the adjusted negative electrode profile for the degraded battery cell, there is an advantage that the positive electrode profile of the degraded battery cell may be easily estimated in a non-destructive manner.