Patents by Inventor Hyungmin Cho
Hyungmin Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230347821Abstract: A device is provided that includes a vision camera, a sensor module, a communication module, an output module, a memory, and a processor operatively connected to the vision camera, the sensor module, the communication module, the output module, and the memory. The processor is configured to connect to an external electronic device via the communication module, receive, from the external electronic device, location information of the external electronic device and determine an expected moving path, recognize an obstacle on the expected moving path based on at least one of the location information of the external electronic device, an image acquired from the vision camera, a sensor value acquired from the sensor module, and information collected from another device located on a road through the communication module, and determine risk of collision between the external electronic device and the obstacle so as to provide a risk notification through the output module.Type: ApplicationFiled: July 5, 2023Publication date: November 2, 2023Inventors: Juyeon YOU, Kyusung KIM, Soojung BAE, Yongjun LIM, Hyungmin CHO, Woonkee HAN
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Publication number: 20230269492Abstract: A method for displaying an image in an electronic device is provided. The method includes obtaining a first image including a plurality of subjects, setting a plurality of sub-regions respectively including the plurality of subjects, obtaining a distance between the plurality of sub-regions, when a distance between a first region and a second region, which are adjacent to each other, among the plurality of sub-regions is greater than or equal to a specified threshold distance, omitting at least a portion of a third region disposed between the first region and the second region in the first image, and displaying a second image obtained by resetting a size of each of the plurality of sub-regions and rearranging each of the plurality of sub-regions.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: Kyuwon KIM, Yusic KIM, Chulsang CHANG, Hyungmin CHO, Jaewoong CHOI
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Patent number: 11641524Abstract: A method for displaying an image in an electronic device is provided. The method includes obtaining a first image including a plurality of subjects, setting a plurality of sub-regions respectively including the plurality of subjects, obtaining a distance between the plurality of sub-regions, when a distance between a first region and a second region, which are adjacent to each other, among the plurality of sub-regions is greater than or equal to a specified threshold distance, omitting at least a portion of a third region disposed between the first region and the second region in the first image, and displaying a second image obtained by resetting a size of each of the plurality of sub-regions and rearranging each of the plurality of sub-regions.Type: GrantFiled: February 5, 2021Date of Patent: May 2, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kyuwon Kim, Yusic Kim, Chulsang Chang, Hyungmin Cho, Jaewoong Choi
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Publication number: 20220222315Abstract: The present disclosure includes a first step of preloading weight values of each filter into respective processing element (PE) chains through a column input link, a second step of supplying an input value to the column input link in the same order as the weight values of the preloaded filters, a third step of starting accumulation in a column output link matching the column input link when a first input value among the input values reaches a top end of the PE chains, a fourth step of moving while further accumulating a product of a facing input value and the weight values of the filter loaded at a corresponding position when the accumulated value moves and faces the input value supplied, and a fifth step of outputting an output value accumulated by multiplication when the accumulated value to be moved reaches a lowest end of the PE chains.Type: ApplicationFiled: January 12, 2022Publication date: July 14, 2022Applicant: Research & Business Foundation Sungkyunkwan UniversityInventor: Hyungmin CHO
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Patent number: 11157239Abstract: A method of verifying randomness of a bitstream is disclosed. The method includes receiving a bitstream consisting of n consecutive bits and dividing the bitstream into a plurality of bit blocks. In this case, n is a natural number of two or greater, each of the bit blocks consists of m consecutive bits, and m is a natural number of two or greater and is smaller than n. Further, the method includes allocating the plurality of bit blocks to a plurality of core groups in a graphics processing unit (GPU), processing the allocated bit blocks in the plurality of core groups in parallel, calculating random number level values of the allocated bit blocks, and determining whether the bitstream has randomness based on the calculated random number level values. Each of the core groups includes a plurality of cores capable of performing identical or similar tasks without separate synchronization.Type: GrantFiled: May 24, 2019Date of Patent: October 26, 2021Assignee: HONGIK UNIVERSITY INDUSTRY-ACADEMIA COOPERATION FOUNDATIONInventors: HyungGyoon Kim, Hyungmin Cho, Changwoo Pyo
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Publication number: 20210250498Abstract: A method for displaying an image in an electronic device is provided. The method includes obtaining a first image including a plurality of subjects, setting a plurality of sub-regions respectively including the plurality of subjects, obtaining a distance between the plurality of sub-regions, when a distance between a first region and a second region, which are adjacent to each other, among the plurality of sub-regions is greater than or equal to a specified threshold distance, omitting at least a portion of a third region disposed between the first region and the second region in the first image, and displaying a second image obtained by resetting a size of each of the plurality of sub-regions and rearranging each of the plurality of sub-regions.Type: ApplicationFiled: February 5, 2021Publication date: August 12, 2021Inventors: Kyuwon KIM, Yusic KIM, Chulsang CHANG, Hyungmin CHO, Jaewoong CHOI
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Publication number: 20190361678Abstract: A method of verifying randomness of a bitstream is disclosed. The method includes receiving a bitstream consisting of n consecutive bits and dividing the bitstream into a plurality of bit blocks. In this case, n is a natural number of two or greater, each of the bit blocks consists of m consecutive bits, and m is a natural number of two or greater and is smaller than n. Further, the method includes allocating the plurality of bit blocks to a plurality of core groups in a graphics processing unit (GPU), processing the allocated bit blocks in the plurality of core groups in parallel, calculating random number level values of the allocated bit blocks, and determining whether the bitstream has randomness based on the calculated random number level values. Each of the core groups includes a plurality of cores capable of performing identical or similar tasks without separate synchronization.Type: ApplicationFiled: May 24, 2019Publication date: November 28, 2019Applicant: Hongik University Industry-Academia Cooperation FoundationInventors: HyungGyoon Kim, Hyungmin Cho, Changwoo Pyo
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Patent number: 8762794Abstract: Methods and systems for cross-layer forgiveness exploitation include executing one or more applications using a processing platform that includes a first reliable processing core and at least one additional processing core having a lower reliability than the first processing core, modifying application execution according to one or more best-effort techniques to improve performance, and controlling parameters associated with the processing platform and the best-effort layer that control performance and error rate such that performance is maximized in a region of low hardware-software interference.Type: GrantFiled: November 18, 2011Date of Patent: June 24, 2014Assignee: NEC Laboratories America, Inc.Inventors: Srimat Chakradhar, Hyungmin Cho, Anand Raghunathan
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Publication number: 20120131389Abstract: Methods and systems for cross-layer forgiveness exploitation include executing one or more applications using a processing platform that includes a first reliable processing core and at least one additional processing core having a lower reliability than the first processing core, modifying application execution according to one or more best-effort techniques to improve performance, and controlling parameters associated with the processing platform and the best-effort layer that control performance and error rate such that performance is maximized in a region of low hardware-software interference.Type: ApplicationFiled: November 18, 2011Publication date: May 24, 2012Applicant: NEC Laboratories America, Inc.Inventors: Srimat Chakradhar, Hyungmin Cho, Anand Raghunathan