Abstract: The semiconductor cell structure includes unit cells that do not protrude from one another along columns and rows. The unit cells include active regions and gate patterns. The semiconductor cell structure also includes dummy patterns and conductive patterns. The gate patterns intersect the active regions. The dummy patterns electrically connect the unit cells. Dummy patterns are disposed at least between gate patterns in the selected unit cell. The conductive patterns are electrically connected to the dummy patterns. The semiconductor cell structure is disposed in a semiconductor device and a semiconductor module.

Abstract: An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads.

Abstract: An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads.

Abstract: A method of fabricating a semiconductor device includes forming a first electrode, sequentially forming a first dielectric film, a conductive film for a second electrode, a second dielectric film, and a conductive film for a third electrode above the first electrode, forming a first pattern on the conductive film for a third electrode, the first pattern defining a second electrode, forming the second electrode by sequentially patterning the conductive film for the third electrode, the second dielectric film, and the conductive film for the second electrode, using the first pattern as an etching mask, partially removing the first pattern to form a second pattern that defines a third electrode, and forming the third electrode by patterning the conductive film for the third electrode, using the second pattern as an etching mask, wherein the third electrode has a width less than that of the second electrode.

Abstract: Disclosed are methods of fabricating semiconductor devices. A method may include forming a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The method may also include forming a mask layer on the third conductive layer, forming a photoresist pattern on the mask layer, and forming at least one middle electrode by patterning the mask layer, the third conductive layer, the second dielectric layer, and the second conductive layer using the photoresist pattern as an etching mask. The method may also include forming a mask pattern by selectively etching a side wall of the patterned mask layer, removing the photoresist pattern, and forming an upper electrode by patterning the third conductive layer using the mask pattern as an etching mask.

Abstract: An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads.

Abstract: A semiconductor device includes a wiring layer that is formed on a substrate and includes a first pad contact region and a second pad contact region, a passivation layer that includes a first opening and a second opening on the wiring layer and a protrusion pattern dividing the first opening and the second opening, and a pad metal pattern that is conformally formed along the first opening, the second opening, and the protrusion pattern of the passivation layer. The first pad contact region is exposed through the first opening and the second pad contact region is exposed through the second opening.

Abstract: A method of fabricating a semiconductor device includes forming a first electrode, sequentially forming a first dielectric film, a conductive film for a second electrode, a second dielectric film, and a conductive film for a third electrode above the first electrode, forming a first pattern on the conductive film for a third electrode, the first pattern defining a second electrode, forming the second electrode by sequentially patterning the conductive film for the third electrode, the second dielectric film, and the conductive film for the second electrode, using the first pattern as an etching mask, partially removing the first pattern to form a second pattern that defines a third electrode, and forming the third electrode by patterning the conductive film for the third electrode, using the second pattern as an etching mask, wherein the third electrode has a width less than that of the second electrode.

Abstract: A non-volatile memory device and method of fabricating same are disclosed. The memory device comprises; a gate insulating film formed on a semiconductor substrate, a floating gate completely covering the gate insulating film, the floating gate comprising a conductive film pattern and a conductive spacer formed at one side of the conductive film pattern, a tunnel insulating film formed on a portion of the conductive film pattern, the conductive spacer, and extending laterally outward over a portion of the semiconductor substrate adjacent the conductive spacer, a control gate formed on the tunnel insulating film, a first impurity region formed within the semiconductor substrate proximate one side of the conductive film pattern opposite the conductive spacer, and a second impurity region formed within the semiconductor substrate proximate one side of the control gate disposed laterally outward from the floating gate.

Abstract: Disclosed are methods of fabricating semiconductor devices. A method may include forming a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer. The method may also include forming a mask layer on the third conductive layer, forming a photoresist pattern on the mask layer, and forming at least one middle electrode by patterning the mask layer, the third conductive layer, the second dielectric layer, and the second conductive layer using the photoresist pattern as an etching mask. The method may also include forming a mask pattern by selectively etching a side wall of the patterned mask layer, removing the photoresist pattern, and forming an upper electrode by patterning the third conductive layer using the mask pattern as an etching mask.

Abstract: A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a vertical portion covering a side wall of the gate pattern, and a lateral portion extending from the bottom of the vertical portion over the source/drain region. Support portions interposed between the L-shaped spacers and the gate pattern support the lateral portions of the L-shaped spacers such that an air gap is defined between at least the lateral portions of the L-shaped spacers and the source/drain regions. The air gap minimizes the parasitic capacitance associated with the gate electrode of the semiconductor device.

Abstract: A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a vertical portion covering a side wall of the gate pattern, and a lateral portion extending from the bottom of the vertical portion over the source/drain region. Support portions interposed between the L-shaped spacers and the gate pattern support the lateral portions of the L-shaped spacers such that an air gap is defined between at least the lateral portions of the L-shaped spacers and the source/drain regions. The air gap minimizes the parasitic capacitance associated with the gate electrode of the semiconductor device.

Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a bottom electrode and a first interconnection layer on a semiconductor substrate, an upper surface of the bottom electrode and an upper surface of the first interconnection layer being level, an interlayer insulating layer having a trench exposing the upper surface of the bottom electrode and a via hole exposing the upper surface of the first interconnection layer, a contact plug formed of a first material inside the via hole and connected to the first interconnection layer, an upper electrode formed of a second material inside the trench on the bottom electrode, the first material being exclusive of the second material, and a dielectric layer interposed between the bottom electrode and the upper electrode, and formed only inside the trench.

Abstract: A semiconductor device includes source/drain regions, a gate pattern disposed on the semiconductor substrate between the source/drain regions, and L-shaped spacers that are used as masks in the forming of the source/drain regions. The L-shaped spacers each include a vertical portion covering a side wall of the gate pattern, and a lateral portion extending from the bottom of the vertical portion over the source/drain region. Support portions interposed between the L-shaped spacers and the gate pattern support the lateral portions of the L-shaped spacers such that an air gap is defined between at least the lateral portions of the L-shaped spacers and the source/drain regions. The air gap minimizes the parasitic capacitance associated with the gate electrode of the semiconductor device.

Abstract: A method for fabricating a semiconductor device and a semiconductor formed by this method, the method including, the steps of sequentially forming a pad oxide film, a polysilicon film, and an antioxidation film on an active region of a semiconductor substrate such that a field region is exposed; etching an exposed portion of the surface of the substrate to a predetermined thickness to form a trench within the substrate; forming a first insulation film along the inner face of the trench by using an oxidation process; forming a stress buffer film on the entire surface of the resultant structure; forming a second insulation film on the stress buffer film such that the trench is sufficiently filled; making the second insulation film planar such that the remaining antioxidation film has a predetermined thickness on the active region of the substrate so as to form a shallow trench isolation within the trench; and sequentially removing the remaining antioxidation film, the polysilicon film, and the pad oxide film.

Abstract: Present invention relates to telecommunication switching systems and methods of packet switching and can be usable at development new high-speed telecommunication devices and equipment as switching structure.

Abstract: In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which suicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.

Abstract: In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which silicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.

Abstract: A method for manufacturing an MDL semiconductor device comprises forming a gate insulating layer and a gate conductive layer in a DRAM device region and a logic device region to provide gate conductive layer patterns which will be respectively formed in the DRAM device region and the logic device region. Next, the gate conductive layer of the logic device region is patterned, and a gate conductive layer pattern is formed only in the logic device region. Spacers are formed on the gate conductive layer patterns, and impurity ions of different conductivity types are twice injected by a process for forming a mask layer pattern and an ion injection process. The first ion injection is performed on one gate conductive layer pattern of the logic device region, and the second ion injection is performed on the gate conductive layer of the DRAM device region and the other gate conductive layer pattern of the logic device region.

Abstract: A method for manufacturing an MDL semiconductor device comprises forming a gate insulating layer and a gate conductive layer in a DRAM device region and a logic device region to provide gate conductive layer patterns which will be respectively formed in the DRAM device region and the logic device region. Next, the gate conductive layer of the logic device region is patterned, and a gate conductive layer pattern is formed only in the logic device region. Spacers are formed on the gate conductive layer patterns, and impurity ions of different conductivity types are twice injected by a process for forming a mask layer pattern and an ion injection process. The first ion injection is performed on one gate conductive layer pattern of the logic device region, and the second ion injection is performed on the gate conductive layer of the DRAM device region and the other gate conductive layer pattern of the logic device region.