Patents by Inventor Hyungrok DO
Hyungrok DO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11451007Abstract: A driving circuit includes an input circuit slice configured to convert a data signal into a first data signal and a second data signal having different DC components. The driving circuit also includes a driver slice configured to output driving current at an output node by generating push current or pull current according to the first data signal and the second data signal, wherein a magnitude of the push current or the pull current is variable.Type: GrantFiled: December 10, 2019Date of Patent: September 20, 2022Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Jeongho Hwang, Hong Seok Choi, Hyungrok Do, Deog-Kyoon Jeong
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Patent number: 11227655Abstract: A semiconductor memory device includes a memory cell array including one or more memory cells each coupled between a wordline and a bitline, a sense amplifier configured to amplify a voltage of a global wordline, a wordline decoder including a plurality of wordline switches coupling the wordline and the global wordline, and a control circuit configured to control the wordline decoder and the sense amplifier.Type: GrantFiled: June 25, 2019Date of Patent: January 18, 2022Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Hyungrok Do, Hong Seok Choi, Deog-Kyoon Jeong
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Patent number: 11087825Abstract: A semiconductor memory device includes a bitline driver configured to drive a global bitline; a memory cell array including a first memory cell that is coupled between a cell wordline and a cell bitline; a bitline decoder including a bitline switch that couples the global bitline and the cell bitline; a wordline decoder including a wordline switch that couples a global wordline and the cell wordline; a sense amplifier configured to output a sensing signal corresponding to a state of the first memory cell based on a voltage of the global bitline; and a control circuit configured to control the bitline driver, the bitline decoder, the wordline decoder and the sense amplifier during a first read operation for the first memory cell.Type: GrantFiled: December 12, 2019Date of Patent: August 10, 2021Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Hong Seok Choi, Hyungrok Do, Deog-Kyoon Jeong
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Patent number: 10950279Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.Type: GrantFiled: August 20, 2019Date of Patent: March 16, 2021Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Deog-Kyoon Jeong, Jung Min Yoon, Hyungrok Do, Dae-Hyun Koh
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Patent number: 10931305Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.Type: GrantFiled: October 22, 2019Date of Patent: February 23, 2021Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Hong Seok Choi, Jeongho Hwang, Hyungrok Do, Deog-Kyoon Jeong
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Publication number: 20200395062Abstract: A semiconductor memory device includes a bitline driver configured to drive a global bitline; a memory cell array including a first memory cell that is coupled between a cell wordline and a cell bitline; a bitline decoder including a bitline switch that couples the global bitline and the cell bitline; a wordline decoder including a wordline switch that couples a global wordline and the cell wordline; a sense amplifier configured to output a sensing signal corresponding to a state of the first memory cell based on a voltage of the global bitline; and a control circuit configured to control the bitline driver, the bitline decoder, the wordline decoder and the sense amplifier during a first read operation for the first memory cell.Type: ApplicationFiled: December 12, 2019Publication date: December 17, 2020Inventors: Hong Seok CHOI, Hyungrok DO, Deog-Kyoon JEONG
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Publication number: 20200335937Abstract: A driving circuit includes an input circuit slice configured to convert a data signal into a first data signal and a second data signal having different DC components. The driving circuit also includes a driver slice configured to output driving current at an output node by generating push current or pull current according to the first data signal and the second data signal, wherein a magnitude of the push current or the pull current is variable.Type: ApplicationFiled: December 10, 2019Publication date: October 22, 2020Applicants: SK hynix Inc., Seoul National University R&DB FoundationInventors: Jeongho HWANG, Hong Seok CHOI, Hyungrok DO, Deog-Kyoon JEONG
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Publication number: 20200321977Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.Type: ApplicationFiled: October 22, 2019Publication date: October 8, 2020Inventors: Hong Seok CHOI, Jeongho HWANG, Hyungrok DO, Deog-Kyoon JEONG
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Publication number: 20200075065Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.Type: ApplicationFiled: August 20, 2019Publication date: March 5, 2020Inventors: Deog-Kyoon JEONG, Jung Min YOON, Hyungrok DO, Dae-Hyun KOH
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Publication number: 20200013459Abstract: A semiconductor memory device includes a memory cell array including one or more memory cells each coupled between a wordline and a bitline, a sense amplifier configured to amplify a voltage of a global wordline, a wordline decoder including a plurality of wordline switches coupling the wordline and the global wordline, and a control circuit configured to control the wordline decoder and the sense amplifier.Type: ApplicationFiled: June 25, 2019Publication date: January 9, 2020Inventors: Hyungrok DO, Hong Seok CHOI, Deog-Kyoon JEONG
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Patent number: 10490259Abstract: An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.Type: GrantFiled: March 30, 2018Date of Patent: November 26, 2019Assignees: SK hynix Inc., Seoul National R&DB FoundationInventors: Deog-Kyoon Jeong, Jung Min Yoon, Hyungrok Do
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Publication number: 20190013060Abstract: An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.Type: ApplicationFiled: March 30, 2018Publication date: January 10, 2019Inventors: Deog-Kyoon JEONG, Jung Min YOON, Hyungrok DO