Patents by Inventor Hyung-Shin Kwon
Hyung-Shin Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060148153Abstract: Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.Type: ApplicationFiled: December 30, 2005Publication date: July 6, 2006Inventors: Hyung-Shin Kwon, Dong-Won Lee, Jun-Beom Park
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Publication number: 20060079060Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided.Type: ApplicationFiled: November 18, 2005Publication date: April 13, 2006Applicant: Samsung Electronics Co., Ltd.Inventor: Hyung-Shin Kwon
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Patent number: 7002223Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided.Type: GrantFiled: July 26, 2002Date of Patent: February 21, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Hyung-Shin Kwon
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Publication number: 20050029664Abstract: An interconnection structure is provided by forming a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode.Type: ApplicationFiled: September 2, 2004Publication date: February 10, 2005Inventors: Won-Seok Cho, Soon-Moon Jung, Sung-Bong Kim, Hyung-Shin Kwon
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Patent number: 6815275Abstract: A method of fabricating an integrated circuit device comprises forming a refractory metal layer on a silicon-containing substrate, processing the refractory metal layer to form an amorphous metal silicide layer, and depositing an insulating material on the amorphous metal silicide layer. The insulating material is deposited at a temperature that maintains at least a portion of the amorphous metal silicide layer in an amorphous state, to form a capping structure that contains the amorphous metal silicide layer. The method further includes crystallizing the contained amorphous metal silicide layer, and forming an etching stop layer on the capping structure.Type: GrantFiled: September 27, 2002Date of Patent: November 9, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-shin Kwon, Won-suek Cho, Byung-jun Hwang
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Patent number: 6806180Abstract: An interconnection structure is provided by foiling a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode.Type: GrantFiled: April 30, 2003Date of Patent: October 19, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Seok Cho, Soon-Moon Jung, Sung-Bong Kim, Hyung-Shin Kwon
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Publication number: 20040198032Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.Type: ApplicationFiled: April 21, 2004Publication date: October 7, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Joon-Yong Joo, Kwang-Ok Koh, Sung-Bong Kim
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Publication number: 20040173854Abstract: Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings.Type: ApplicationFiled: March 5, 2004Publication date: September 9, 2004Inventors: Hyung-Shin Kwon, Soon-Moon Jung
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Patent number: 6767814Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.Type: GrantFiled: March 18, 2002Date of Patent: July 27, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Joon-Yong Joo, Kwang-Ok Koh, Sung-Bong Kim
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Publication number: 20040018725Abstract: An interconnection structure is provided by foiling a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode.Type: ApplicationFiled: April 30, 2003Publication date: January 29, 2004Inventors: Won-Seok Cho, Soon-Moon Jung, Sung-Bong Kim, Hyung-Shin Kwon
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Patent number: 6635539Abstract: A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are sequentially stacked on a predetermined region of a semiconductor substrate. Impurities are implanted into the semiconductor substrate to form a source/drain region. A first metal silicide layer is selectively formed on the surface of the source/drain region. The silicidation resistant layer pattern is then removed to expose the gate electrode. A second metal silicide layer is selectively formed on the exposed gate electrode. Consequently, the first metal silicide layer can be formed of a metal silicide layer having superior tolerance with respect to junction spiking. Also, the second metal silicide layer can be formed of another metal silicide layer having a low variation of resistivity due to the variation of the line width of the gate electrode.Type: GrantFiled: April 22, 2002Date of Patent: October 21, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Do-Hyung Kim
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Publication number: 20030092228Abstract: A method of fabricating an integrated circuit device comprises forming a refractory metal layer on a silicon-containing substrate, processing the refractory metal layer to form an amorphous metal suicide layer, and depositing an insulating material on the amorphous metal silicide layer. The insulating material is deposited at a temperature that maintains at least a portion of the amorphous metal silicide layer in an amorphous state, to form a capping structure that contains the amorphous metal silicide layer. The method further includes crystallizing the contained amorphous metal silicide layer, and forming an etching stop layer on the capping structure.Type: ApplicationFiled: September 27, 2002Publication date: May 15, 2003Inventors: Hyung-Shin Kwon, Won-Suek Cho, Byung-Jun Hwang
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Patent number: 6551887Abstract: The present invention provides a method of forming a semiconductor device spacer. In the method, a gate pattern is formed on a semiconductor substrate, and a first insulation layer, a second insulation layer, and a third insulation layer are sequentially formed over substantially the entire surface of the resultant structure. The second and third insulation layers are formed of the same material under a first pressure and a second pressure higher than the first pressure, respectively, and preferably of silicon nitride, using a low pressure chemical vapor deposition (LPCVD) technique. The third and second insulation layers are sequentially, anisotropically etched until the first insulation layer is exposed, thereby forming a spacer and a second insulation pattern. The spacer is selectively removed by an isotropic etching method, to minimize the recessed extent of the second insulation pattern. The exposed first insulation layer is etched to form a first insulation pattern.Type: GrantFiled: July 16, 2002Date of Patent: April 22, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Joon-Yong Joo
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Publication number: 20030045061Abstract: The present invention provides a method of forming a semiconductor device spacer. In the method, a gate pattern is formed on a semiconductor substrate, and a first insulation layer, a second insulation layer, and a third insulation layer are sequentially formed over substantially the entire surface of the resultant structure. The second and third insulation layers are formed of the same material under a first pressure and a second pressure higher than the first pressure, respectively, and preferably of silicon nitride, using a low pressure chemical vapor deposition (LPCVD) technique. The third and second insulation layers are sequentially, anisotropically etched until the first insulation layer is exposed, thereby forming a spacer and a second insulation pattern. The spacer is selectively removed by an isotropic etching method, to minimize the recessed extent of the second insulation pattern. The exposed first insulation layer is etched to form a first insulation pattern.Type: ApplicationFiled: July 16, 2002Publication date: March 6, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Joon-Yong Joo
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Publication number: 20030025163Abstract: The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided.Type: ApplicationFiled: July 26, 2002Publication date: February 6, 2003Applicant: Samsung Electronics Co., Ltd.Inventor: Hyung-Shin Kwon
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Publication number: 20020197805Abstract: A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are sequentially stacked on a predetermined region of a semiconductor substrate. Impurities are implanted into the semiconductor substrate to form a source/drain region. A first metal silicide layer is selectively formed on the surface of the source/drain region. The silicidation resistant layer pattern is then removed to expose the gate electrode. A second metal silicide layer is selectively formed on the exposed gate electrode. Consequently, the first metal silicide layer can be formed of a metal silicide layer having superior tolerance with respect to junction spiking. Also, the second metal silicide layer can be formed of another metal silicide layer having a low variation of resistivity due to the variation of the line width of the gate electrode.Type: ApplicationFiled: April 22, 2002Publication date: December 26, 2002Applicant: Samsung Electronics Co., Ltd.Inventors: Hyung-Shin Kwon, Do-Hyung Kim
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Publication number: 20020130372Abstract: The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate insulation layer. An impurity region is formed in the active region adjacent the gate electrode. A silicide thin film such as a cobalt silicide thin film is formed to a thickness of less than approximately 200 Å in the impurity region.Type: ApplicationFiled: March 18, 2002Publication date: September 19, 2002Applicant: Samsung Electronics Co., LtdInventors: Hyung-Shin Kwon, Joon-Yong Joo, Kwang-Ok Koh, Sung-Bong Kim