Abstract: A serial data port in a dual port memory device adapted to receive incoming serial data and transfer the incoming serial data to a general data register, comprising; a plurality of data latches storing a portion of the incoming serial data, each data latch comprising a plurality of shift registers, and each shift register being responsive to one of a plurality of sequentially generated shift register control signals, and a plurality of transfer gates, each transfer gate gating the incoming serial data into a corresponding data latch in responsive to a one of a plurality of sequentially generated data latch control signals, wherein each data latch control signal defines a time period, and the plurality of shift register control signals is sequentially generated within the time period.

Abstract: A dual-slope waveform generation circuit without a DC path and with decreased layout area including a pull-up and pull-down resistor, a transmission gate and an inverter. An input signal IN is applied to the pull-up transistor, to each gates of MOS transistors M.sub.1, M.sub.2 composing of the inverter A, and to drains of MOS transistors M.sub.3, M.sub.4 composing of the transmission gate B. A common node in the inverter is connected to the gate of the N type MOS transistor in the transmission gate. The sources of the transistors M.sub.3, M.sub.4 are connected to the gate of the pull-down transistor. An output signal OUT is applied to the gate of the transistor M.sub.4 and the signal is fed back.