Patents by Inventor Hyung Suk Lee
Hyung Suk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250126854Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.Type: ApplicationFiled: December 20, 2024Publication date: April 17, 2025Inventors: Jae-hyun PARK, Kye-hyun BAEK, Yong-ho JEON, Cheol KIM, Sung-il PARK, Yun-il LEE, Hyung-suk LEE
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Patent number: 12279458Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.Type: GrantFiled: September 28, 2023Date of Patent: April 15, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Joong Gun Oh, Sung Il Park, Jae Hyun Park, Hyung Suk Lee, Eun Sil Park, Yun Il Lee
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Publication number: 20250066672Abstract: A pyrolysis system for waste includes: a pyrolysis apparatus configured to receive waste and generate combustible gas by pyrolyzing the received waste; an emulsification apparatus connected to the pyrolysis apparatus and configured to produce pyrolysis oil by cooling condensable gas among the combustible gas generated by the pyrolysis apparatus and discharge non-condensable gas; and a combustion furnace connected to the emulsification apparatus and configured to receive and combust the non-condensable gas discharged from the emulsification apparatus, where the combustion furnace is configured to generate hot air by combusting the non-condensable gas, and supply the hot air to the pyrolysis apparatus to pyrolyze the waste.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Applicant: HANWHA MOMENTUM CORPORATIONInventors: Hyung Suk LEE, Do Hyung KIM, Ho Jung KANG, Jang Ho YU, Ju Ho JEONG
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Patent number: 12218193Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.Type: GrantFiled: November 17, 2021Date of Patent: February 4, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-hyun Park, Kye-hyun Baek, Yong-ho Jeon, Cheol Kim, Sung-il Park, Yun-il Lee, Hyung-suk Lee
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Patent number: 12134268Abstract: The inventive concept provides an inkjet printing method. The inkjet printing method for discharging an ink on a substrate using a head having a plurality of nozzles formed thereon includes determining a grade of nozzles by measuring a discharge performance of the nozzles, which is a grading step; selecting a use nozzle that can participate in printing the substrate among the nozzles based on the grade determined at the grading step, which is a nozzle selecting step; and discharging the ink on the substrate using at least one nozzle among use nozzles, which is a printing step.Type: GrantFiled: July 19, 2022Date of Patent: November 5, 2024Assignee: SEMES CO., LTD.Inventors: Dong Hyun Jun, Woon Sang Baek, Sang Hyuk Yun, Keun Hwa Yang, Hyung Suk Lee, Cheol Hyung Cho
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Publication number: 20240055432Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.Type: ApplicationFiled: September 28, 2023Publication date: February 15, 2024Inventors: Joong Gun Oh, Sung Il Park, Jae Hyun Park, Hyung Suk Lee, Eun Sil Park, Yun Il Lee
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Patent number: 11804490Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.Type: GrantFiled: November 23, 2021Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joong Gun Oh, Sung Il Park, Jae Hyun Park, Hyung Suk Lee, Eun Sil Park, Yun Il Lee
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Publication number: 20230122379Abstract: A semiconductor device includes an active pattern with a lower pattern and sheet patterns spaced apart from the lower pattern, a gate structure on the lower pattern and having a gate electrode and a gate insulating film that surround each of the sheet patterns, a gate capping pattern on the gate structure, a gate etching stop pattern between the gate capping pattern and the gate structure, a gate spacer along a sidewall of the gate capping pattern, a source/drain pattern on the gate structure, a gate contact through the gate capping pattern and connected to the gate electrode, upper surfaces of the gate contact and gate spacer being coplanar, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern.Type: ApplicationFiled: August 2, 2022Publication date: April 20, 2023Inventors: Shin Cheol MIN, Keon Yong CHEON, Myung Dong KO, Yong Hee PARK, Sang Hyeon LEE, Dong Won KIM, Woo Seung SHIN, Hyung Suk LEE
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Publication number: 20230035323Abstract: The inventive concept provides an inkjet printing method. The inkjet printing method for discharging an ink on a substrate using a head having a plurality of nozzles formed thereon includes determining a grade of nozzles by measuring a discharge performance of the nozzles, which is a grading step; selecting a use nozzle that can participate in printing the substrate among the nozzles based on the grade determined at the grading step, which is a nozzle selecting step; and discharging the ink on the substrate using at least one nozzle among use nozzles, which is a printing step.Type: ApplicationFiled: July 19, 2022Publication date: February 2, 2023Applicant: SEMES CO., LTD.Inventors: Dong Hyun JUN, Woon Sang BAEK, Sang Hyuk YUN, Keun Hwa YANG, Hyung Suk LEE, Cheol Hyung CHO
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Publication number: 20230019860Abstract: A semiconductor device including a substrate; first and second active patterns on the substrate, extending in a first direction and spaced apart in a second direction; gate electrodes on the first and second active patterns and extending in the second direction; a first gate separation structure between the first and second active patterns, extending in the first direction, and separating the gate electrodes; and a first element separation structure between the gate electrodes, extending in the second direction, and separating the second active pattern, wherein a distance to a first side of a first portion of the first gate separation structure is smaller than a distance to the first side of a second portion of the first gate separation structure, and a distance to the second side of the first portion is smaller than a distance from the second active pattern to the second side of the second portion.Type: ApplicationFiled: April 12, 2022Publication date: January 19, 2023Inventors: Myung-Dong KO, Keon Yong CHEON, Dong Won KIM, Hyun Suk KIM, Sang Hyeon LEE, Hyung Suk LEE
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Publication number: 20220349073Abstract: An electrochemical electrode according to the present invention may prevent agglomeration and desorption of a catalyst even when a catalyst in a particle form is used, because a protective layer containing hydrogel is used, such that stability may be secured, thereby implementing an electrode having a long duration.Type: ApplicationFiled: April 29, 2022Publication date: November 3, 2022Inventors: Joo Ho MOON, Hyung suk LEE, Byung Jun KANG, Jei Wan TAN, Don Yeong KANG, Kyung Min KIM
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Publication number: 20220116011Abstract: The present invention relates to an acoustic wave transmission device for moving a fluid or fine particles inside the fluid to a desired position using acoustic waves, and more particularly, to an acoustic wave transmission device including an acoustic wave transmission medium that minimizes acoustic wave interference due to the acoustic wave transmission medium by reducing reflection and refraction that may be generated when acoustic waves pass through the acoustic wave transmission medium in which a fluid is accommodated, and a manufacturing method of the acoustic wave transmission medium.Type: ApplicationFiled: October 13, 2021Publication date: April 14, 2022Inventors: Hyung Suk LEE, Jun Ki BAEK, Chan Ryeol RHYOU, Byung Jun KANG
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Publication number: 20220085016Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Inventors: Joong Gun OH, Sung Il PARK, Jae Hyun PARK, Hyung Suk LEE, Eun Sil PARK, Yun Il LEE
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Publication number: 20220077285Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Jae-hyun PARK, Kye-hyun BAEK, Yong-ho JEON, Cheol KIM, Sung-il PARK, Yun-il LEE, Hyung-suk LEE
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Patent number: 11271156Abstract: A method for fabricating an electronic device including a semiconductor memory includes forming a chalcogenide layer, forming a first conductive layer on the chalcogenide layer, and increasing a density of an interface between the chalcogenide layer and the first conductive layer by injecting or irradiating ions onto the interface.Type: GrantFiled: May 9, 2019Date of Patent: March 8, 2022Assignee: SK hynix Inc.Inventor: Hyung Suk Lee
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Patent number: 11211450Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.Type: GrantFiled: July 12, 2018Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-hyun Park, Kye-hyun Baek, Yong-ho Jeon, Cheol Kim, Sung-il Park, Yun-il Lee, Hyung-suk Lee
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Patent number: 11195833Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a first gate electrode extending in a second direction intersecting the first direction on the fin type pattern, a source/drain region on a side wall of the first gate electrode and in the fin type pattern, a separation structure extending in the first direction on the substrate, the separation structure including a first trench and being spaced apart from the fin type pattern and separating the first gate electrode, an interlayer insulating layer on a side wall of the separation structure and covering the source/drain region, the interlayer insulating layer including a second trench having a lower surface lower than a lower surface of the first trench, and a contact connected to the source/drain region and filling the first trench and the second trench.Type: GrantFiled: December 13, 2018Date of Patent: December 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joong Gun Oh, Sung Il Park, Jae Hyun Park, Hyung Suk Lee, Eun Sil Park, Yun Il Lee
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Patent number: 10937700Abstract: A semiconductor device includes a first semiconductor pattern doped with first impurities on a substrate, a first channel pattern on the first semiconductor pattern, second semiconductor patterns doped with second impurities contacting upper edge surfaces, respectively, of the first channel pattern, and a first gate structure surrounding at least a portion of a sidewall of the first channel pattern.Type: GrantFiled: May 1, 2017Date of Patent: March 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mirco Cantoro, Yun-Il Lee, Hyung-Suk Lee, Yeon-Cheol Heo, Byoung-Gi Kim, Chang-Min Yoe, Seung-Chan Yun, Dong-Hun Lee
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Patent number: 10714599Abstract: A semiconductor device including a first fin type pattern and a second fin type pattern which protrude from a substrate and are spaced apart from each other to extend in a first direction, a dummy fin type pattern protruding from the substrate between the first fin type pattern and the second fin type pattern, a first gate structure extending in a second direction intersecting with the first direction, on the first fin type pattern, a second gate structure extending in the second direction, on the second fin type pattern, and a capping pattern extending in the second direction, on the first gate structure and the second gate structure, wherein the capping pattern includes a separation part which is in contact with an upper surface of the dummy fin type pattern, and the dummy fin type pattern and the separation part separate the first gate structure and the second gate structure.Type: GrantFiled: January 16, 2019Date of Patent: July 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yun II Lee, Sung II Park, Jae Hyun Park, Hyung Suk Lee
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Patent number: 10692931Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes stack structures, a gap-fill layer filling spaces between the stack structures, and nanopores located in the gap-fill layer. Each of the stack structures includes a memory pattern. The nanopores are distributed in a portion of the gap-fill layer that is located at a level corresponding to where the memory pattern is located in each of the stack structures.Type: GrantFiled: August 22, 2018Date of Patent: June 23, 2020Assignee: SK hynix Inc.Inventor: Hyung Suk Lee