Patents by Inventor Hyung-woo Chung

Hyung-woo Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240080320
    Abstract: A server according to an embodiment includes a processor configured to receive a friend add request for a target account from a user terminal accessed with a user account; based on one of the user account and the target account being a protected account, transmit an approval request for the friend add request to a protector account connected to the protected account; and based on receiving a reply to the approval request from the protector terminal, add the target account to a friend list of the user account.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Inventors: You Jin KIM, Jung Woo CHOI, Jenog Ryeol CHOI, Joong Seon KIM, Hong Chan YUN, Ju Ho CHUNG, Do Hyun YOUN, Hyung Min KIM, Hyun Ok CHOI, Chun Ho KIM, Soo Beom KIM, Min Jeong KIM, Chang Oh HEO, Eun Soo HEO
  • Patent number: 8785998
    Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-woo Chung, Yong-chul Oh, Yoo-sang Hwang, Gyo-young Jin, Hyeong-sun Hong, Dae-ik Kim
  • Patent number: 8362536
    Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-woo Chung, Yong-chul Oh, Yoo-sang Hwang, Gyo-young Jin, Hyeong-sun Hong, Dae-ik Kim
  • Publication number: 20110284939
    Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.
    Type: Application
    Filed: October 14, 2010
    Publication date: November 24, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-woo Chung, Yong-chul OH, Yoo-sang HWANG, Gyo-young JIN, Hyeong-sun HONG, Dae-ik KIM