Patents by Inventor Hyung-youl PARK

Hyung-youl PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573774
    Abstract: In case of forming electrodes for electronic device using a two-dimensional semiconductor, a two-dimensional semiconductor layer doped into n-type or p-type is formed on a substrate, a first area and a second area of the doped two-dimensional semiconductor layer is patterned into a predetermined pattern shape, and a first electrode and a second electrode are formed on the patterned first and second areas, respectively.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 25, 2020
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Hyung Youl Park, Jeong Hoon Kim, Woo Young Choi
  • Patent number: 10128126
    Abstract: The present disclosure relates to a method of doping a 2-dimensional semiconductor. The method of doping a 2-dimensional semiconductor includes: forming an insulating layer including photosensitive particles on a substrate; moving the photosensitive particles included in the insulating layer to a surface of the insulating layer through a heat treatment; forming a 2-dimensional semiconductor layer on the insulating layer; and doping a 2-dimensional semiconductor material included in the 2-dimensional semiconductor layer by exposing the 2-dimensional semiconductor material to a light corresponding to an absorption wavelength of the photosensitive particles included in the insulating layer.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: November 13, 2018
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jin Hong Park, Hyung Youl Park
  • Publication number: 20170243998
    Abstract: In case of forming electrodes for electronic device using a two-dimensional semiconductor, a two-dimensional semiconductor layer doped into n-type or p-type is formed on a substrate, a first area and a second area of the doped two-dimensional semiconductor layer is patterned into a predetermined pattern shape, and a first electrode and a second electrode are formed on the patterned first and second areas, respectively.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 24, 2017
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Jin Hong PARK, Hyung Youl PARK, Jeong Hoon KIM, Woo Young CHOI
  • Publication number: 20170125263
    Abstract: The present disclosure relates to a method of doping a 2-dimensional semiconductor. The method of doping a 2-dimensional semiconductor includes: forming an insulating layer including photosensitive particles on a substrate; moving the photosensitive particles included in the insulating layer to a surface of the insulating layer through a heat treatment; forming a 2-dimensional semiconductor layer on the insulating layer; and doping a 2-dimensional semiconductor material included in the 2-dimensional semiconductor layer by exposing the 2-dimensional semiconductor material to a light corresponding to an absorption wavelength of the photosensitive particles included in the insulating layer.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 4, 2017
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Jin Hong PARK, Hyung Youl PARK
  • Patent number: 9570684
    Abstract: Example embodiments relate to methods of doping a 2-dimensional semiconductor. The method includes forming a semiconductor layer on a substrate, implanting ions into the semiconductor layer, forming a doped layer formed of a 2-dimensional semiconductor layer or an organic semiconductor layer on the semiconductor layer, and doping the doped layer by diffusing the ions of the semiconductor layer into the doped layer through annealing the substrate.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: February 14, 2017
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Jin-hong Park, Hyung-youl Park, Jae-woo Shim, Jae-ho Lee
  • Patent number: 9318556
    Abstract: Provided are graphene transistors having a tunable barrier. The graphene transistor includes a semiconductor substrate, an insulating thin film disposed on the semiconductor substrate, a graphene layer on the insulating thin film, a first electrode connected to an end of the graphene layer, a second electrode that is separate from an other end of the graphene layer and contacts the semiconductor substrate, a gate insulating layer covering the graphene layer, and a gate electrode on the gate insulating layer, wherein an energy barrier is formed between the semiconductor substrate and the graphene layer.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: April 19, 2016
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Jin-hong Park, Jae-woo Shim, Hyung-youl Park, Jae-ho Lee
  • Publication number: 20150214304
    Abstract: Provided are graphene transistors having a tunable barrier. The graphene transistor includes a semiconductor substrate, an insulating thin film disposed on the semiconductor substrate, a graphene layer on the insulating thin film, a first electrode connected to an end of the graphene layer, a second electrode that is separate from an other end of the graphene layer and contacts the semiconductor substrate, a gate insulating layer covering the graphene layer, and a gate electrode on the gate insulating layer, wherein an energy barrier is formed between the semiconductor substrate and the graphene layer.
    Type: Application
    Filed: July 10, 2014
    Publication date: July 30, 2015
    Applicant: Sungkyunkwan University Research & Business Foundation
    Inventors: Jin-hong PARK, Jae-woo SHIM, Hyung-youl PARK, Jae-ho LEE
  • Publication number: 20150214482
    Abstract: Example embodiments relate to methods of doping a 2-dimensional semiconductor. The method includes forming a semiconductor layer on a substrate, implanting ions into the semiconductor layer, forming a doped layer formed of a 2-dimensional semiconductor layer or an organic semiconductor layer on the semiconductor layer, and doping the doped layer by diffusing the ions of the semiconductor layer into the doped layer through annealing the substrate.
    Type: Application
    Filed: July 24, 2014
    Publication date: July 30, 2015
    Applicant: Sungkyunkwan University Research & Business Foundation
    Inventors: Jin-hong PARK, Hyung-youl PARK, Jae-woo SHIM, Jae-ho LEE