Abstract: An analog-to-digital converting apparatus includes a first stage converter which performs a first analog-to-digital conversion on an input analog signal during a first stage period, a second stage converter which receives a first residue from the first stage converter amplified by a first gain and which performs a second analog-to-digital conversion during a second stage period, and a recombination logic circuit which combines a first output signal from the first stage converter and a second output signal from the second stage converter into an output digital signal that corresponds to the input analog signal. The second stage converter generates a second stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle in the second stage period, and generates a second output signal of a second sub-cycle subsequent to the first sub-cycle based on the second stage feedback signal.

Abstract: An analog-to-digital converting apparatus includes a first stage converter which performs a first analog-to-digital conversion on an input analog signal during a first stage period, a second stage converter which receives a first residue from the first stage converter amplified by a first gain and which performs a second analog-to-digital conversion during a second stage period, and a recombination logic circuit which combines a first output signal from the first stage converter and a second output signal from the second stage converter into an output digital signal that corresponds to the input analog signal. The second stage converter generates a second stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle in the second stage period, and generates a second output signal of a second sub-cycle subsequent to the first sub-cycle based on the second stage feedback signal.

Abstract: A circuit for digital-to-analog conversion using a plurality of 3-level cells includes a circuit for digital-to-analog conversion using a plurality of 3-level cells mutually independently providing positive electricity, providing negative electricity, or floating. The circuit including a preprocess circuit and a shift circuit. The preprocess circuit is configured to receive thermometer code data generated from signed binary data and generate a shift count for shifting a cell pointer pointing to one of the plurality of 3-level cells for dynamic element matching (DEM) from the thermometer code data. The shift circuit is configured to store the cell pointer and shift the stored cell pointer according to the shift count. The shifted cell pointer is shifted in proportion to an absolute value of the binary data in a direction depending on a sign of the binary data.

Abstract: A circuit for digital-to-analog conversion using a plurality of 3-level cells includes a circuit for digital-to-analog conversion using a plurality of 3-level cells mutually independently providing positive electricity, providing negative electricity, or floating. The circuit including a preprocess circuit and a shift circuit. The preprocess circuit is configured to receive thermometer code data generated from signed binary data and generate a shift count for shifting a cell pointer pointing to one of the plurality of 3-level cells for dynamic element matching (DEM) from the thermometer code data. The shift circuit is configured to store the cell pointer and shift the stored cell pointer according to the shift count. The shifted cell pointer is shifted in proportion to an absolute value of the binary data in a direction depending on a sign of the binary data.

Abstract: Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode.

Abstract: Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode.

Abstract: Provided is a band-gap reference voltage generator for low-voltage operation and high precision. The band-gap reference voltage generator minimizes voltage drop by connecting resistors in parallel to bipolar transistors, and cancels temperature dependence by properly adjusting a resistor of an output stage, so that it can provide a stable reference voltage that is unaffected by a change in temperature in spite of a low power supply voltage. Further, the band-gap reference voltage generator minimizes variation of the reference voltage caused by offset noise by switching of input and output voltages at input and output stages of a feedback amplifier, so that it can provide a precise reference voltage.

Abstract: Provided is a band-gap reference voltage generator for low-voltage operation and high precision. The band-gap reference voltage generator minimizes voltage drop by connecting resistors in parallel to bipolar transistors, and cancels temperature dependence by properly adjusting a resistor of an output stage, so that it can provide a stable reference voltage that is unaffected by a change in temperature in spite of a low power supply voltage. Further, the band-gap reference voltage generator minimizes variation of the reference voltage caused by offset noise by switching of input and output voltages at input and output stages of a feedback amplifier, so that it can provide a precise reference voltage.