Patents by Inventor Hyung Woo YU

Hyung Woo YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11625524
    Abstract: An integrated circuit includes a first region corresponding to a first circuit and including a first dummy pattern and a first signal pattern which are spaced apart from each other by a width of a spacer in a conductive layer to extend in parallel in a first horizontal direction and a second region corresponding to a second circuit which is the same as the first circuit and including a second dummy pattern and a second signal pattern which are spaced apart from each other by the width of the spacer in the conductive layer to extend in parallel in the first horizontal direction. The first signal pattern and the second signal pattern are configured so that a first signal and a second signal corresponding to each other in the first circuit and the second circuit are respectively applied to the first signal pattern and the second signal pattern.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-joon An, Hyung-woo Yu, Sun-ah Kim, Jae-woo Yang
  • Publication number: 20200218146
    Abstract: An integrated circuit includes a first region corresponding to a first circuit and including a first dummy pattern and a first signal pattern which are spaced apart from each other by a width of a spacer in a conductive layer to extend in parallel in a first horizontal direction and a second region corresponding to a second circuit which is the same as the first circuit and including a second dummy pattern and a second signal pattern which are spaced apart from each other by the width of the spacer in the conductive layer to extend in parallel in the first horizontal direction. The first signal pattern and the second signal pattern are configured so that a first signal and a second signal corresponding to each other in the first circuit and the second circuit are respectively applied to the first signal pattern and the second signal pattern.
    Type: Application
    Filed: July 19, 2019
    Publication date: July 9, 2020
    Inventors: Hyo-joon AN, Hyung-woo YU, Sun-ah KIM, Jae-woo YANG
  • Patent number: 9171514
    Abstract: A method of muxing data by using clock signals having different timings and an apparatus performing the method are provided. Storing and muxing (or dividing) the data are simultaneously performed. The apparatus includes a first latch circuit arranging data blocks, which are input in series, in parallel in response to non-overlapping latch control signals and a second latch circuit latching the data blocks arranged in parallel simultaneously in response to a clock signal.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yang Wook Kim, Suk Yun Woo, Jun Ho Song, Seong Jong Yoo, Dong Min Lee, Kyung Gyu Park, Hyung Woo Yu
  • Publication number: 20140062995
    Abstract: A method of muxing data by using clock signals having different timings and an apparatus performing the method are provided. Storing and muxing (or dividing) the data are simultaneously performed. The apparatus includes a first latch circuit arranging data blocks, which are input in series, in parallel in response to non-overlapping latch control signals and a second latch circuit latching the data blocks arranged in parallel simultaneously in response to a clock signal.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 6, 2014
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Yang Wook KIM, Suk Yun WOO, Jun Ho SONG, Seong Jong YOO, Dong Min LEE, Kyung Gyu PARK, Hyung Woo YU