Abstract: A display device includes a substrate, a first display element which is disposed on the substrate, and a plurality of diffraction patterns which are disposed on a path of light emitted from the first display element and arranged along a direction with a first period. when a width of a cross section of one of the plurality of diffraction patterns is defined as a first length, the first period and the first length satisfy Inequality (1): 0.4 ? d ? 1 / DP ? 1 ? 1 , ( 1 ) where DP1 is the first period, and d1 is the first length.

Abstract: The present invention relates to an intra prediction method and apparatus. The image decoding method according to the present invention may comprise decoding information on intra prediction; and generating a prediction block by performing intra prediction for a current block based on the information on intra prediction. The information on intra prediction may include information on an intra prediction mode, and the intra prediction mode may include a curved intra prediction mode.

Abstract: The present invention relates to an intra prediction method and apparatus. The image decoding method according to the present invention may comprise decoding information on intra prediction; and generating a prediction block by performing intra prediction for a current block based on the information on intra prediction. The information on intra prediction may include information on an intra prediction mode, and the intra prediction mode may include a curved intra prediction mode.

Abstract: A memory device includes a base die configured to transmit transmission data that are driven to a first voltage range through a transmission line based on base data, and a core die configured to generate core data by shifting a voltage level of the transmission data received through the transmission line to a second voltage range.

Abstract: An image encoding/decoding method and apparatus for predicting a second color component block using a first color component block are provided. An image decoding method of the present invention comprises deriving a prediction parameter using the first color component block, and predicting the second color component block using the derived prediction parameter.

Abstract: Disclosed are a source driver capable of achieving high speed and high resolution and a display driving circuit including the same. The source driver may include: a first channel group and a second channel group configured to output source driving signals; a first gradation voltage divider configured to generate first gradation voltages using gamma reference voltages and provide the first gradation voltages to the first channel group; and a second gradation voltage divider configured to generate second gradation voltages having the same level as the first gradation voltages using the gamma reference voltages, and provide the second gradation voltages to the second channel group. The first and second gradation voltage dividers are connected to a gamma reference voltage generator configured to provide the gamma reference voltages, and receive the gamma reference voltages having the same voltage range from the gamma reference voltage generator.

Abstract: Disclosed are a source driver capable of achieving high speed and high resolution and a display driving circuit including the same. The source driver may include: a first channel group and a second channel group configured to output source driving signals; a first gradation voltage divider configured to generate first gradation voltages using gamma reference voltages and provide the first gradation voltages to the first channel group; and a second gradation voltage divider configured to generate second gradation voltages having the same level as the first gradation voltages using the gamma reference voltages, and provide the second gradation voltages to the second channel group. The first and second gradation voltage dividers are connected to a gamma reference voltage generator configured to provide the gamma reference voltages, and receive the gamma reference voltages having the same voltage range from the gamma reference voltage generator.

Abstract: The present invention relates to a display apparatus which drives a display panel to display an image, and a driving circuit thereof. The display apparatus includes a timing controller configured to provide a control option having a value for compensating for pixel data and a gray scale, and a driving circuit configured to combines the control option and the pixel data and output an output voltage.

Abstract: A wafer storage container includes a shell body including a first side body and a second side body that face, an upper body connected with upper parts of the first side body and the second side body, a rear body connected with an end of one side of each of the first side body and the second side body, and a lower body connected with lower parts of the first side body and the second side body, and configured to define an internal space together with the first side body, the second side body, the upper body, and the rear body.

Abstract: A wafer container includes a base, a guide, a cover, a locking member and a sealing member. The base includes an installing surface thereon. The guide is disposed on the installing surface of the base. The guide is configured to confine a plurality of wafers horizontally stacked upon the installing surface of the base. The cover is configured to cover the installing surface. The locking member is configured to lock the cover to the base. The sealing member is configured to create an air-tight seal between the locking member and the guide.

Abstract: Provided is a display driving circuit capable of achieving high speed and high resolution by improving an output slew rate. The display driving circuit may include: a gradation voltage generation unit including a plurality of resistor strings corresponding to a plurality of groups into which channels corresponding to display data are grouped, the plurality of resistor strings being configured to provide gradation voltages to digital-analog converters (DACs) corresponding to the respective channels of the corresponding groups; and a display driving unit including the DACs and buffers corresponding to the respective channels, wherein the DACs convert the corresponding display data into data voltages using the gradation voltages, and the buffers provide the corresponding data voltages as source driving signals to a display panel.

Abstract: A source driver may include: a transmission line configured to transmit an output signal of a sample and hold circuit which stores pixel information of an organic light emitting diode (OLED) cell; an amplifier is formed a first offset voltage at an input terminal by a parasitic capacitor of the transmission line; and an offset voltage storage unit configured to store the first offset voltage outputted from the amplifier as a second offset voltage while the transmission of the output signal of the sample and hold circuit through the transmission line is turned off, and offset the first offset voltage by providing the second offset voltage to the input terminal of the amplifier when the output signal of the sample and hold circuit is transmitted through the transmission line.

Abstract: The present invention relates to a display apparatus which drives a display panel to display an image, and a driving circuit thereof. The display apparatus includes a timing controller configured to provide a control option having a value for compensating for pixel data and a gray scale, and a driving circuit configured to combines the control option and the pixel data and output an output voltage.

Abstract: A sample and hold circuit may include: a main sample and hold circuit configured to sample and hold pixel information of an organic light emitting diode (OLED) cell, and output a first output signal; and a dummy sample and hold circuit configured to sample and hold a reference voltage in synchronization with the main sample and hold circuit, and output a second output signal for offsetting a switching noise signal contained in the first output signal.

Abstract: A circuit for driving an organic light emitting diode display includes a display panel that displays an image by using organic light emitting diodes disposed at intersection areas of a plurality of gate lines and a plurality of data lines; a threshold voltage detection control unit that supplies a precharge voltage by sequentially turning on transistors for threshold voltage detection, which are connected among the data lines and the organic light emitting diodes on the display panel, in units of horizontal lines, and enables threshold voltages to be detected; and a source driver that detects threshold voltages of all organic light emitting diodes arranged on a corresponding horizontal line, and repeats an operation, as necessary, for sampling/holding the detected threshold voltages through M sample/hold circuits, converting the sampled/held threshold voltages into digital signals, and storing the digital signals in a memory.

Abstract: A display driving circuit may include: an output buffer unit including a plurality of output buffer pairs, wherein among the plurality of output buffer pairs, each of first output buffers has a first voltage driving potential, and each of second output buffers has a second voltage driving potential; an output switch unit configured to directly connect the plurality of output buffer pairs to a plurality of output line pairs or cross and connect the plurality of output buffer pairs to the plurality of output line pairs; and a charge sharing switch unit configured to connect first output lines corresponding to the first output buffers, and connect second output lines corresponding to the second output buffers. Through this configuration, the display driving circuit can reduce power consumption and heat generation.

Abstract: An encoding/decoding apparatus and method for parallel correction of in-loop pixels based on complexity using a video parameter may include a complexity measuring unit to measure a complexity of an in-loop pixel correction process, using video codec parameter information, in a video codec, and a core allocating unit to evenly distribute jobs associated with the in-loop pixel correction process, using the measured complexity.

Abstract: A wafer storage container includes a shell body including a first side body and a second side body that face, an upper body connected with upper parts of the first side body and the second side body, a rear body connected with an end of one side of each of the first side body and the second side body, and a lower body connected with lower parts of the first side body and the second side body, and configured to define an internal space together with the first side body, the second side body, the upper body, and the rear body.