Patents by Inventor Hyunil Bae

Hyunil Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063196
    Abstract: A semiconductor device has a semiconductor die, substrate, and plurality of first conductive pillars formed over the semiconductor die or substrate. Alternatively, the first conductive pillars formed over the semiconductor die and substrate. An electrical component is disposed over the semiconductor die. The electrical component can be a double-sided IPD. The semiconductor die and electrical component are disposed over the substrate. A shielding frame is disposed over the semiconductor die. A plurality of second conductive pillars is formed over a first surface of the electrical component. A plurality of third conductive pillars is formed over a second surface of the electrical component opposite the first surface of the electrical component. A bump cap can be formed over a distal end of the conductive pillars. The substrate has a cavity and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and substrate.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: TaeKeun Lee, Hyunil Bae
  • Patent number: 9559046
    Abstract: A semiconductor device is made by providing a first semiconductor die having a plurality of contact pads formed over a first surface of the first semiconductor die and having a plurality of through-silicon vias (TSVs) formed within the first semiconductor die. A second semiconductor die is mounted to the first surface of the first semiconductor die using a plurality of solder bumps. At least one of the solder bumps is in electrical communication with the TSVs in the first semiconductor die. The second semiconductor die is mounted to a printed circuit board (PCB) using an adhesive material. A plurality of solder bumps is formed to connect the contact pads of the first semiconductor die to the PCB. An encapsulant is deposited over the first semiconductor die and the second semiconductor die. An interconnect structure is formed over a back surface of the PCB.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: January 31, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Hyunil Bae, Youngchul Kim, Myungkil Lee
  • Patent number: 8816487
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate, having a component side and a system side; mounting a first integrated circuit die on the component side of the package substrate; mounting a second integrated circuit die on the component side of the package substrate; mounting an internal package, having an internal die, over the first integrated circuit die; coupling chip interconnects between the first integrated circuit die, the second integrated circuit die, the internal die, the component side, or a combination thereof, and forming a stacked package body by encapsulating the component side, the first integrated circuit die, the second integrated circuit die, the internal package, and the chip interconnects.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: August 26, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Hyunil Bae, YoungChul Kim, Myung Kil Lee
  • Patent number: 8476135
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base carrier having a base carrier hole from a base carrier interconnection side to a base carrier device side; mounting a base integrated circuit over the base carrier; forming an encapsulation over the base carrier covering the base integrated circuit, the encapsulation having an encapsulation top side and having an encapsulation hole directly over the base carrier hole; and forming an interconnection structure as a single integral structure through the base carrier hole and the encapsulation hole, the interconnection structure directly on the encapsulation top side and directly on the base carrier interconnection side.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 2, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: JinGwan Kim, Hyunil Bae
  • Publication number: 20120299168
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base carrier having a base carrier hole from a base carrier interconnection side to a base carrier device side; mounting a base integrated circuit over the base carrier; forming an encapsulation over the base carrier covering the base integrated circuit, the encapsulation having an encapsulation top side and having an encapsulation hole directly over the base carrier hole; and forming an interconnection structure as a single integral structure through the base carrier hole and the encapsulation hole, the interconnection structure directly on the encapsulation top side and directly on the base carrier interconnection side.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Inventors: JinGwan Kim, Hyunil Bae
  • Publication number: 20100065948
    Abstract: A semiconductor device is made by providing a first semiconductor die having a plurality of contact pads formed over a first surface of the first semiconductor die and having a plurality of through-silicon vias (TSVs) formed within the first semiconductor die. A second semiconductor die is mounted to the first surface of the first semiconductor die using a plurality of solder bumps. At least one of the solder bumps is in electrical communication with the TSVs in the first semiconductor die. The second semiconductor die is mounted to a printed circuit board (PCB) using an adhesive material. A plurality of solder bumps is formed to connect the contact pads of the first semiconductor die to the PCB. An encapsulant is deposited over the first semiconductor die and the second semiconductor die. An interconnect structure is formed over a back surface of the PCB.
    Type: Application
    Filed: September 12, 2008
    Publication date: March 18, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Hyunil Bae, Youngchul Kim, Myungkil Lee
  • Publication number: 20090236723
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate, having a component side and a system side; mounting a first integrated circuit die on the component side of the package substrate; mounting a second integrated circuit die on the component side of the package substrate; mounting an internal package, having an internal die, over the first integrated circuit die; coupling chip interconnects between the first integrated circuit die, the second integrated circuit die, the internal die, the component side, or a combination thereof, and forming a stacked package body by encapsulating the component side, the first integrated circuit die, the second integrated circuit die, the internal package, and the chip interconnects.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 24, 2009
    Inventors: Hyunil Bae, YoungChul Kim, Myung Kil Lee
  • Publication number: 20070268660
    Abstract: A spacerless semiconductor package chip stacking system is provided having a substrate. The substrate has at least one window therethrough. A first semiconductor device is attached face down on the top of the substrate. A second semiconductor device is attached face up on the back of the first semiconductor device. The first semiconductor device is electrically connected through the window to the bottom of the substrate. The second semiconductor device is electrically connected to the substrate.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 22, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Seungyun Ahn, Youngcheol Kim, Haengcheol Choi, Myung Kil Lee, JoHyun Bae, Hyunil Bae, Junwoo Myung