Abstract: Provided is an apparatus for automatically classifying an input sound source according to a preset criterion and are an apparatus and method for automatically classifying a sound source according to a set criterion by using deep learning. The apparatus for classifying a sound source includes a processor and a memory connected to the processor and storing a deep learning algorithm and original sound data, wherein the memory stores program instructions executable by the processor to generate n pieces of image data corresponding to the original sound data according to a preset method, generate training image data corresponding to the original sound data by using the n pieces of image data, train the deep learning algorithm by using the training image data, and classify target sound data according to a preset criterion by using the deep learning algorithm, wherein the n is a natural number greater than or equal to 2.

Abstract: The present invention provides a method for preventing or treating a liver disease selected from the group consisting of non-alcoholic fatty liver, non-alcoholic steatohepatitis and hepatic fibrosis comprising administrating at least one selected from the group consisting of an Ssu72 peptide, a polynucleotide encoding the Ssu72 peptide, and an expression vector comprising the polynucleotide.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

Abstract: A method of manufacturing a semiconductor device includes forming first sacrificial cores on a first region of a lower structure and second sacrificial cores on a second region of the lower structure, forming spacers on side walls of the first sacrificial cores and side walls of the second sacrificial cores, forming a protective pattern covering the second sacrificial cores on the second region of the lower structure, removing the first sacrificial cores from the first region, and etching the lower structure using the spacers on the first region, and the second sacrificial cores and the spacers on the second region. By using only spacers as an etching mask in the first region and the sacrificial cores with the spacers as an etching mask in the second region, patterns with different widths are formed simultaneously on the first and second regions.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: A method of manufacturing a semiconductor device includes forming first sacrificial cores on a first region of a lower structure and second sacrificial cores on a second region of the lower structure, forming spacers on side walls of the first sacrificial cores and side walls of the second sacrificial cores, forming a protective pattern covering the second sacrificial cores on the second region of the lower structure, removing the first sacrificial cores from the first region, and etching the lower structure using the spacers on the first region, and the second sacrificial cores and the spacers on the second region.

Abstract: A semi-submersible marine structure is described. The structure includes a hull including a pontoon, a deck disposed above the pontoon, and a plurality of columns supporting the deck from the pontoon. The structure also includes a plurality of tendons supporting the hull from a seabed. The pontoon has the shape of a circular ring, and the plurality of tendons are arranged at regular intervals along an external circumferential surface of the pontoon.

Abstract: Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.

Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

Abstract: Semiconductor devices are provided. The semiconductor device includes an active fin which extends along a first direction and has a protruding shape, a gate structure which is disposed on the active fin to extend along a second direction intersecting the first direction, and a spacer which is disposed on at least one side of the gate structure, wherein the gate structure includes a first area and a second area which is adjacent to the first area in the second direction, wherein a first width of the first area in the first direction is different from a second width of the second area in the first direction, and the spacer extends continuously along both the first area and the second area.

Abstract: A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.

Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.