Patents by Inventor Hyunkook Park
Hyunkook Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240062819Abstract: A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.Type: ApplicationFiled: April 5, 2023Publication date: February 22, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Hyunkook PARK, Ahreum KIM, Pansuk KWAK
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Patent number: 11908533Abstract: Disclosed is an operation method of a memory device which includes floating a first driving line corresponding to a first word line from the first word line and precharging the first driving line with a first voltage, floating the first driving line from the first voltage to sense a first voltage variation of the first driving line, storing the first voltage variation in a first capacitor, electrically connecting the first driving line to the first word line and precharging the first driving line and the first word line with the first voltage, floating the first driving line and the first word line from the first voltage to sense a second voltage variation of the first driving line and the first word line, and outputting a first detection signal corresponding to a first leakage current through the first word line based on the first voltage variation and the second voltage variation.Type: GrantFiled: April 24, 2022Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hyunkook Park
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Publication number: 20230140995Abstract: A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.Type: ApplicationFiled: September 9, 2022Publication date: May 11, 2023Inventors: Hyunkook Park, Sara Choi
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Publication number: 20220415420Abstract: Disclosed is an operation method of a memory device which includes floating a first driving line corresponding to a first word line from the first word line and precharging the first driving line with a first voltage, floating the first driving line from the first voltage to sense a first voltage variation of the first driving line, storing the first voltage variation in a first capacitor, electrically connecting the first driving line to the first word line and precharging the first driving line and the first word line with the first voltage, floating the first driving line and the first word line from the first voltage to sense a second voltage variation of the first driving line and the first word line, and outputting a first detection signal corresponding to a first leakage current through the first word line based on the first voltage variation and the second voltage variation.Type: ApplicationFiled: April 24, 2022Publication date: December 29, 2022Inventor: HYUNKOOK PARK
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Patent number: 10529432Abstract: A data storage device according to example embodiments of inventive concepts includes a nonvolatile memory and a memory controller. In the nonvolatile memory, one read unit is configured to store a plurality of codewords. If a fail occurs in one or more codewords stored in the nonvolatile memory, the memory controller may search a read voltage of the nonvolatile memory using a correctable codeword. The data storage device according to example embodiments may predict an optimum read voltage level without performing a valley search operation.Type: GrantFiled: January 25, 2017Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Hyunkook Park
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Patent number: 9875788Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.Type: GrantFiled: March 25, 2010Date of Patent: January 23, 2018Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han
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Patent number: 9865330Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.Type: GrantFiled: November 4, 2010Date of Patent: January 9, 2018Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Mingu Kang, Hyunkook Park, Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han, Lixin Ge, Zhongze Wang
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Publication number: 20170235633Abstract: A data storage device according to example embodiments of inventive concepts includes a nonvolatile memory and a memory controller. In the nonvolatile memory, one read unit is configured to store a plurality of codewords. If a fail occurs in one or more codewords stored in the nonvolatile memory, the memory controller may search a read voltage of the nonvolatile memory using a correctable codeword. The data storage device according to example embodiments may predict an optimum read voltage level without performing a valley search operation.Type: ApplicationFiled: January 25, 2017Publication date: August 17, 2017Inventor: Hyunkook PARK
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Patent number: 9685237Abstract: Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.Type: GrantFiled: June 22, 2016Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hyunkook Park, Yeongtaek Lee, Daeseok Byeon
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Publication number: 20170110197Abstract: Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.Type: ApplicationFiled: June 22, 2016Publication date: April 20, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Hyunkook PARK, Yeongtaek LEE, Daeseok BYEON
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Patent number: 8447547Abstract: In a particular embodiment, a method is disclosed that estimates a total static noise margin of a bit cell of a memory. The method includes determining a correlation coefficient of a left static noise margin of the bit cell as compared to a right static noise margin of the bit cell and estimating a total static noise margin of the bit cell by evaluating an analytical function based on the correlation coefficient.Type: GrantFiled: June 17, 2009Date of Patent: May 21, 2013Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Seung-Chul Song, Hyunkook Park
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Publication number: 20120113708Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.Type: ApplicationFiled: November 4, 2010Publication date: May 10, 2012Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Mingu Kang, Hyunkook Park, Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han, Lixin Ge, Zhongze Wang
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Publication number: 20110235406Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicants: QUALCOMM INCORPORATED, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han
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Publication number: 20100324850Abstract: In a particular embodiment, a method is disclosed that estimates a total static noise margin of a bit cell of a memory. The method includes determining a correlation coefficient of a left static noise margin of the bit cell as compared to a right static noise margin of the bit cell and estimating a total static noise margin of the bit cell by evaluating an analytical function based on the correlation coefficient.Type: ApplicationFiled: June 17, 2009Publication date: December 23, 2010Applicants: QUALCOMM INCORPORATED, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Seung-Chul Song, Hyunkook Park