Abstract: A memory device and an operating method thereof adjust a slope of a word line voltage. The memory device includes a memory cell array including a plurality of cell strings, a voltage generating circuit configured to generate a word line voltage provided to a plurality of word lines, and a control logic configured to output a slope control signal adjusting a voltage level variation characteristic of the word line voltage provided from the voltage generating circuit, wherein, during a prepulse period of a read operation of the memory device, a slope of a first word line voltage provided to an edge group including one or more word lines, the edge group adjacent to a string selection line is greater than a slope of a second word line voltage provided to a center group including one or more word lines in a center region.

Abstract: The present disclosure relates to methods of operating non-volatile memory devices. An example read operation method of a non-volatile memory device includes applying a first read voltage, generated from a voltage generator, to a selected wordline, performing a first sensing node develop operation associated with the first read voltage, and performing a first sensing operation associated with the first read voltage. While the first sensing node develop operation is performed, the voltage generator generates a second read voltage based on the selected wordline being disconnected from the voltage generator and thereby being floated.

Abstract: A method of programming data in a nonvolatile memory device includes setting a state ordering to a first state ordering, the state ordering representing a relationship between a plurality of states and data values of multi-bit data, performing, based on the first state ordering, a program operation on target memory cells of the plurality of memory cells, swapping the state ordering from the first state ordering to a second state ordering different from the first state ordering, performing, based on the second state ordering, the program operation on the target memory cells, re-swapping the state ordering from the second state ordering to the first state ordering, and performing, based on the first state ordering, the program operation on the target memory cells. Each memory cell of a plurality of memory cells of the nonvolatile memory device is programmed to have one of the plurality of states.

Abstract: According to some embodiments of the inventive concept, there is provided a non-volatile memory device comprising: a memory cell array; a pass transistor circuit electrically connected to the memory cell array; a block select line group including a plurality of block select lines, wherein the plurality of block select lines comprises a first block select line and a second block select line, each of which extends in a first direction on a first layer, and the block select line group is electrically connected to the pass transistor circuit; and a first metal line extending in a second direction on a second layer, wherein the second layer is on the first layer, wherein at least one block select line includes at least one twist pattern that changes a path of the at least one block select line in a hole of the first metal line.

Abstract: A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.

Abstract: An operating method of a non-volatile memory device including a plurality of cell strings connected to a plurality of word lines, string select lines, and ground select lines includes applying a program voltage to a selected word line among the word lines during a program execution period, determining a discharge voltage by comparing the program voltage with a negative discharge reference voltage during the program execution period, applying a precharge voltage, which is less than the program voltage and greater than the discharge voltage, to the string select lines up to a first time point during a verify period following the program execution period, and applying the discharge voltage to a substrate of a string select transistor, which is connected to an unselected string select line among the string select lines, up to a second time point after the first time point during the verify period.

Abstract: A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.

Abstract: Disclosed is an operation method of a memory device which includes floating a first driving line corresponding to a first word line from the first word line and precharging the first driving line with a first voltage, floating the first driving line from the first voltage to sense a first voltage variation of the first driving line, storing the first voltage variation in a first capacitor, electrically connecting the first driving line to the first word line and precharging the first driving line and the first word line with the first voltage, floating the first driving line and the first word line from the first voltage to sense a second voltage variation of the first driving line and the first word line, and outputting a first detection signal corresponding to a first leakage current through the first word line based on the first voltage variation and the second voltage variation.

Abstract: A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.

Abstract: Disclosed is an operation method of a memory device which includes floating a first driving line corresponding to a first word line from the first word line and precharging the first driving line with a first voltage, floating the first driving line from the first voltage to sense a first voltage variation of the first driving line, storing the first voltage variation in a first capacitor, electrically connecting the first driving line to the first word line and precharging the first driving line and the first word line with the first voltage, floating the first driving line and the first word line from the first voltage to sense a second voltage variation of the first driving line and the first word line, and outputting a first detection signal corresponding to a first leakage current through the first word line based on the first voltage variation and the second voltage variation.

Abstract: A data storage device according to example embodiments of inventive concepts includes a nonvolatile memory and a memory controller. In the nonvolatile memory, one read unit is configured to store a plurality of codewords. If a fail occurs in one or more codewords stored in the nonvolatile memory, the memory controller may search a read voltage of the nonvolatile memory using a correctable codeword. The data storage device according to example embodiments may predict an optimum read voltage level without performing a valley search operation.

Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

Abstract: A data storage device according to example embodiments of inventive concepts includes a nonvolatile memory and a memory controller. In the nonvolatile memory, one read unit is configured to store a plurality of codewords. If a fail occurs in one or more codewords stored in the nonvolatile memory, the memory controller may search a read voltage of the nonvolatile memory using a correctable codeword. The data storage device according to example embodiments may predict an optimum read voltage level without performing a valley search operation.

Abstract: Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.

Abstract: Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.

Abstract: In a particular embodiment, a method is disclosed that estimates a total static noise margin of a bit cell of a memory. The method includes determining a correlation coefficient of a left static noise margin of the bit cell as compared to a right static noise margin of the bit cell and estimating a total static noise margin of the bit cell by evaluating an analytical function based on the correlation coefficient.

Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.

Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

Abstract: In a particular embodiment, a method is disclosed that estimates a total static noise margin of a bit cell of a memory. The method includes determining a correlation coefficient of a left static noise margin of the bit cell as compared to a right static noise margin of the bit cell and estimating a total static noise margin of the bit cell by evaluating an analytical function based on the correlation coefficient.