Abstract: The present disclosure provides a light-emitting display apparatus including a substrate including a first region and a second region, a first thin-film transistor (TFT) disposed in the first region of the substrate and including a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode, a second TFT disposed in the second region of the substrate and including a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode, at least one insulating layer between the first semiconductor pattern and the second semiconductor pattern, a first blocking layer below the first semiconductor pattern, and a second blocking layer below the second semiconductor pattern.

Abstract: A display apparatus can include an adhesive layer disposed on the substrate, a pixel driver chip disposed on the adhesive layer and including a plurality of pads disposed on an upper surface thereof, a planarization surrounding side surfaces of the pixel driver chip, first wires disposed on the planarization layer, and pad contact layers disposed on a plurality of pads of the pixel driver chip. Here, the pad contact layers and the first wires can have the same thickness and can be composed of the same conductive material layer.

Abstract: Disclosed is a display apparatus including a substrate; an insulating layer disposed on the substrate; a wiring layer disposed on the insulating layer; and a side surface protective layer disposed on a side surface of the wiring layer and having an electrical insulation property, wherein the wiring layer has a stack structure in which a plurality of layers are stacked. In this regard, the side surface protective layer covers a side surface of each of at least some of the plurality of layers of the stack structure.

Abstract: The present disclosure provides a light-emitting display apparatus including a substrate including a first region and a second region, a first thin-film transistor (TFT) disposed in the first region of the substrate and including a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode, a second TFT disposed in the second region of the substrate and including a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode, at least one insulating layer between the first semiconductor pattern and the second semiconductor pattern, a first blocking layer below the first semiconductor pattern, and a second blocking layer below the second semiconductor pattern.

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

Abstract: A display apparatus is disclosed. The display apparatus according to the present disclosure may include a substrate including an active area and a non-active area around the active area, a first shield layer disposed on the substrate, a first thin film transistor including a first semiconductor layer on the first shield layer, a first etch stopper on the first semiconductor layer, a second thin film transistor including a second semiconductor layer on the substrate, and a second etch stopper on the second semiconductor layer.

Abstract: Provided is a display device. The display device comprises a first flexible substrate, a second flexible substrate including a first area, a second area, and a third area, and an intermediate layer between the first flexible substrate and the second flexible substrate. A plurality of pixels is disposed in the first area, and the plurality of pixels includes a first transistor including a polycrystalline semiconductor and a first gate electrode, a second transistor including an oxide semiconductor and a second gate electrode composed of a first metal layer, a second metal layer, and a third metal layer, and a third transistor including the polycrystalline semiconductor disposed in the second area, and a plurality of dams, a first line, a second line, and a cathode are disposed in the third area, and the cathode extends to the first area and the second area.

Abstract: A light emitting display device can include a first thin film transistor including a first semiconductor pattern, a first gate electrode, and first source and drain electrodes; a second thin film transistor including a second semiconductor pattern, a second gate electrode, and second source and drain electrodes; a storage capacitor including a first storage capacitor electrode and a second storage capacitor electrode; and a light emitting element layer electrically connected to the second thin film transistor. The first storage capacitor electrode can be disposed in the same layer as the first gate electrode, and the second storage capacitor electrode can be disposed in the same layer as the second gate electrode.

Abstract: An organic light emitting display device including both a polycrystalline semiconductor element and an oxide semiconductor element, and a method of manufacturing the display device are disclosed. In order to solve the damage of an oxide semiconductor pattern during a heat treatment process in the process of forming the oxide semiconductor element, until the process of forming the polycrystalline semiconductor element is completed, after one portion of a connection electrode connecting a polycrystalline semiconductor pattern to source and drain electrodes is formed in advance, then by forming the other portion of the connection electrode for completing the connection between the source and drain electrodes to the polycrystalline semiconductor pattern in the process of forming the oxide semiconductor element, the connection electrode can have a connection node between two edges thereof, and thereby, the performance of the oxide semiconductor element can be improved.

Abstract: The present disclosure provides a light-emitting display apparatus including a substrate including a first region and a second region, a first thin-film transistor (TFT) disposed in the first region of the substrate and including a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode, a second TFT disposed in the second region of the substrate and including a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode, at least one insulating layer between the first semiconductor pattern and the second semiconductor pattern, a first blocking layer below the first semiconductor pattern, and a second blocking layer below the second semiconductor pattern.

Abstract: An organic light-emitting diode (OLED) display device using hybrid type thin-film transistors (TFTs) is disclosed. The OLED display device includes an etch stopper film on a semiconductor pattern to prevent over etching of the semiconductor pattern located on a lower position and source and drain electrodes are brought in direct contact with the semiconductor pattern while passing through the etch stopper film to prevent malfunction of the TFTs due to surface resistance due to the etch stopper film. Thus, characteristics of the TFTs and process stability are secured.

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

Abstract: Example embodiments disclose a vertical memory device and method of manufacturing the same. The device may include a plurality of gate electrodes and a plurality of insulation patterns and a channel that penetrates a first gate electrode and a first insulation pattern. The device may have a charge storage structure including a tunnel insulation pattern, a charge trapping pattern, and a blocking pattern that are sequentially stacked from an outer sidewall of a channel. The device may have a buried pattern structure that is surrounded by the tunnel insulation pattern and the charge trapping pattern. The charge trapping pattern may include a first vertically sloped portion having a first thickness in the horizontal direction and a second vertically sloped portion having a second thickness in the horizontal direction, and the first thickness may be less than or equal to the second thickness.

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

Abstract: An integrated circuit device includes a plurality of conductive lines extending in a horizontal direction parallel to a main surface of a substrate and overlapping one another in a vertical direction vertical to the main surface, on the substrate, a plurality of insulation layers each between two adjacent conductive lines of the plurality of conductive lines to extend in the horizontal direction, a channel layer extending in the vertical direction in a channel hole passing through the plurality of conductive lines and the plurality of insulation layers, and a plurality of outer blocking dielectric layers between the plurality of conductive lines and the channel layer, in at least some of the plurality of conductive lines, wherein a width of each of the plurality of outer blocking dielectric layers in the horizontal direction increases toward the main surface.

Abstract: Example embodiments disclose a vertical memory device and method of manufacturing the same. The device may include a plurality of gate electrodes and a plurality of insulation patterns and a channel that penetrates a first gate electrode and a first insulation pattern. The device may have a charge storage structure including a tunnel insulation pattern, a charge trapping pattern, and a blocking pattern that are sequentially stacked from an outer sidewall of a channel. The device may have a buried pattern structure that is surrounded by the tunnel insulation pattern and the charge trapping pattern. The charge trapping pattern may include a first vertically sloped portion having a first thickness in the horizontal direction and a second vertically sloped portion having a second thickness in the horizontal direction, and the first thickness may be less than or equal to the second thickness.

Abstract: The present invention relates to a method for growing a nitride semiconductor epitaxial layer, which comprises the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature, thereby, it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate.

Abstract: The present invention relates to a method for growing a nitride semiconductor epitaxial layer, which comprises the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature, thereby, it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate.