Patents by Inventor Hyun-Su Sim

Hyun-Su Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967529
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: April 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Patent number: 11710706
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: July 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Publication number: 20210366837
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Patent number: 11107773
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Su Sim, Yoon-Sung Kim, Yun-Hee Kim, Byung-Moon Bae, Jun-Ho Yoon
  • Publication number: 20210057278
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Application
    Filed: November 10, 2020
    Publication date: February 25, 2021
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Patent number: 10854517
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Publication number: 20200168556
    Abstract: A semiconductor device includes a semiconductor substrate having a scribe lane defined therein. A plurality of semiconductor chips is formed on an upper surface of the semiconductor substrate. At least one conductive structure is arranged on an upper surface of the semiconductor substrate, within the scribe lane thereof. A fillet is arranged on at least one side surface of the conductive structure. The fillet is configured to induce a cut line which spreads along the scribe lane, through a central portion of the conductive structure.
    Type: Application
    Filed: June 13, 2019
    Publication date: May 28, 2020
    Inventors: HYUN-SU SIM, YOON-SUNG KIM, YUN-HEE KIM, BYUNG-MOON BAE, JUN-HO YOON
  • Patent number: 10651105
    Abstract: Provided is a semiconductor chip capable of withstanding damage such as cracks created in the fabrication process. A semiconductor chip according to the inventive concept includes: a semiconductor substrate including a residual scribe lane surrounding a die region and a periphery of a die of the die region, a passivation layer covering a portion above the semiconductor substrate, a cover protection layer covering a portion of the passivation layer and the die region, and a cover protection layer formed integrally with a buffering protection layer covering a portion of the residual scribe lane, wherein the buffering protection layer includes a corner protection layer in contact with a portion of an edge adjacent to a corner of the semiconductor substrate, and an extending protection layer extending along the residual scribe lane from the corner protection layer and in contact with the cover protection layer.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-Hee Kim, Yoon-Sung Kim, Byung-Moon Bae, Hyun-Su Sim
  • Publication number: 20200058551
    Abstract: Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
    Type: Application
    Filed: March 20, 2019
    Publication date: February 20, 2020
    Inventors: Byung-moon Bae, Yoon-sung Kim, Yun-hee Kim, Hyun-su Sim, Jun-ho Yoon, Jung-ho Choi
  • Publication number: 20200020604
    Abstract: Provided is a semiconductor chip capable of withstanding damage such as cracks created in the fabrication process. A semiconductor chip according to the inventive concept includes: a semiconductor substrate including a residual scribe lane surrounding a die region and a periphery of a die of the die region, a passivation layer covering a portion above the semiconductor substrate, a cover protection layer covering a portion of the passivation layer and the die region, and a cover protection layer formed integrally with a buffering protection layer covering a portion of the residual scribe lane, wherein the buffering protection layer includes a corner protection layer in contact with a portion of an edge adjacent to a corner of the semiconductor substrate, and an extending protection layer extending along the residual scribe lane from the corner protection layer and in contact with the cover protection layer.
    Type: Application
    Filed: January 21, 2019
    Publication date: January 16, 2020
    Inventors: Yun-Hee Kim, Yoon-Sung Kim, Byung-Moon Bae, Hyun-Su Sim