Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.

Abstract: A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.

Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals.

Abstract: A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.

Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.

Abstract: A delay circuit for a clock signal includes a first signal generator, a first inverting circuit, a second signal generator and a second inverting circuit. The first signal generator is configured to generate a plurality of first switching signals based on a delay code. The first inverting circuit includes a plurality of first inverters that are selectively turned on in response to the plurality of first switching signals, respectively, and is configured to adjust a first delay time for both of a first edge and a second edge of the clock signal. The second signal generator is configured to generate a plurality of second switching signals based on a duty code. The second inverting circuit includes a plurality of second pull-up units and a plurality of second pull-down units, respective ones of the plurality of second pull-up units or respective ones of the plurality of second pull-down units are selectively turned on in response to respective ones of the plurality of second switching signals.