Patents by Inventor Hyunsuk CHUN
Hyunsuk CHUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12235379Abstract: An electronic device according to various embodiments of the present disclosure may include a plurality of antenna arrays and at least one processor operatively connected to the plurality of antenna arrays. The at least one processor may transmit a first radio signal including a specific polarization, generated through a first antenna array of the plurality of antenna arrays. The at least one processor may receive a second radio signal which is a reflected signal of the first radio signal and includes the specific polarization, generated through a second antenna array different from the first antenna array of the plurality of antenna arrays. The at least one processor may identify external objects around the electronic device on the basis of the second radio signal. Other various embodiments may be possible.Type: GrantFiled: January 12, 2022Date of Patent: February 25, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Kyungrok Lee, Minhong Do, Seongjin Park, Seokwoo Lee, Sukchan Hong, Jaebong Chun, Hyunsuk Choi
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Patent number: 12237567Abstract: According to various embodiments of the disclosure, an electronic device may include: a first housing, a second housing, a printed circuit board (PCB), and a wireless communication circuit, wherein the first housing may include a first surface and a second surface perpendicular to the first surface at a first edge, and a first conductive area, and the first conductive area may include a first portion of a first slit extending from a point on the first surface to the first edge, a third surface of the second housing may include a second conductive area, and the second conductive area may include a second slit, wherein, in a first state, at least a portion of the first portion of the first slit may overlap the second slit when viewed in a second direction perpendicular to the first surface of the first housing, and wherein the wireless communication circuit may be configured to transmit and/or receive a signal of a first frequency band based on an electrical path including the first portion.Type: GrantFiled: December 16, 2022Date of Patent: February 25, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hojin Jung, Hyunsuk Kim, Kyungmoon Seol, Seongyong An, Hyoungtak Cho, Youngmin Ji, Jaebong Chun, Hochul Hwang
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Publication number: 20240363473Abstract: The present invention is directed to semiconductor devices and integrated circuit packaging. In a specific embodiment, a semiconductor device with a heat spreader structure is provided. The heat spreader is configured to couple to a second layer to establish an effective thermal dissipation path for heat generated from a hot spot of a circuit. The second layer comprises a first portion and a second portion. The first portion is coupled to the hot spot. The heat spreader comprises a third portion and a fourth portion. The third portion comprises a protrusion coupled to the first portion via a first side surface. There are other embodiments as well.Type: ApplicationFiled: April 28, 2023Publication date: October 31, 2024Inventors: Hyunsuk Chun, Reza Sharifi, Kian Yeow Gan, Nicole A. Butel, Jin Seong Choi
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Publication number: 20240339437Abstract: Semiconductor device assemblies are provided with one or more layers of thermally conductive material disposed between adjacent semiconductor dies in a vertical stack. The thermally conductive material can be configured to conduct heat generated by one or more of the semiconductor dies in laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), or via adhering a film comprising the layer of thermally conductive material to one or more of the semiconductor dies.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Inventors: Hyunsuk Chun, Xiaopeng Qu
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Patent number: 12028962Abstract: A semiconductor component system includes a motherboard and a cooling system mounted to the motherboard. The cooling system includes sidewalls projecting from the motherboard. A sub-motherboard extends between the sidewalls and is spaced apart from the motherboard. The sidewalls and the sub-motherboard define a cooling channel over the motherboard. A connector is attached to the sub-motherboard and is configured to receive a semiconductor device daughterboard. The connector has contacts to electrically couple the semiconductor device daughterboard to the sub-motherboard.Type: GrantFiled: August 15, 2022Date of Patent: July 2, 2024Assignee: Micron Technology, Inc.Inventors: Xiaopeng Qu, Hyunsuk Chun
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Publication number: 20240203827Abstract: Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.Type: ApplicationFiled: January 18, 2024Publication date: June 20, 2024Inventors: Xiaopeng Qu, Hyunsuk Chun, Eiichi Nakano
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Publication number: 20240203898Abstract: An EM shielding structure for a semiconductor package is embedded in a through hole of a core layer of the semiconductor package. The EM shielding structure may include multiple vias formed by a copper plating operation. Additionally, a metal way surrounds the EM shielding structures and prevents, along with a dielectric material, unwanted EM radiation (passing through the vias) from emanating throughout the semiconductor package. The EM shielding structure can also take the form of an insert that is adhered to the core layer at a through hole of the core layer.Type: ApplicationFiled: December 19, 2022Publication date: June 20, 2024Applicant: Avago Technologies International Sales Pte. LimitedInventors: Jin Seong CHOI, Hyunsuk Chun, Sampath Karikalan, Kwok Cheung Tsang, Wen Hsien Huang, Hsi-Wei Wang, Chia Yuan Yu
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Patent number: 12015011Abstract: Semiconductor device assemblies are provided with one or more layers of thermally conductive material disposed between adjacent semiconductor dies in a vertical stack. The thermally conductive material can be configured to conduct heat generated by one or more of the semiconductor dies in laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), or via adhering a film comprising the layer of thermally conductive material to one or more of the semiconductor dies.Type: GrantFiled: December 27, 2021Date of Patent: June 18, 2024Assignee: Micron Technology, Inc.Inventors: Hyunsuk Chun, Xiaopeng Qu
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Patent number: 11915997Abstract: Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.Type: GrantFiled: August 11, 2020Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Xiaopeng Qu, Hyunsuk Chun, Eiichi Nakano
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Patent number: 11887920Abstract: Embodiments of a redistribution layer structure comprise a low-k dielectric material and incorporating a reinforcement structure proximate and inward of a peripheral edge thereof, the reinforcement structure comprising conductive material electrically isolated from conductive paths through the RDL structure. Semiconductor packages including an embodiment of the RDL structure and methods of fabricating such RDL structures are also disclosed.Type: GrantFiled: November 19, 2020Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Hyunsuk Chun, Chan H. Yoo, Tracy N. Tennant
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Patent number: 11848282Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.Type: GrantFiled: August 16, 2022Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
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Patent number: 11688658Abstract: A semiconductor device having a semiconductor die, a redistribution layer (RDL), and an encapsulant. The RDL layer can be formed on a first surface of the semiconductor die. The encapsulant can enclose a second surface and side surfaces of the semiconductor die. The encapsulant can enclose side portions of the RDL.Type: GrantFiled: March 16, 2021Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventors: Hyunsuk Chun, Shams U. Arifeen, Chan H. Yoo, Tracy N. Tennant
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Patent number: 11676932Abstract: Semiconductor devices having interconnect structures with narrowed portions configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include an end portion away from the semiconductor die, the end portion having a first cross-sectional area. The pillar structure can further include a narrowed portion between the end portion and the semiconductor die, the narrowed portion having a second cross-sectional area less than the first-cross-sectional area of the end portion. A bond material can be coupled to the end portion of the pillar structure.Type: GrantFiled: March 2, 2020Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Hyunsuk Chun, Thiagarajan Raman
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Publication number: 20230154823Abstract: Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.Type: ApplicationFiled: January 13, 2023Publication date: May 18, 2023Inventors: Hyunsuk Chun, Xiaopeng Qu, Chan H. Yoo
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Patent number: 11616028Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.Type: GrantFiled: October 5, 2020Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Shams U. Arifeen, Hyunsuk Chun, Sheng Wei Yang, Keizo Kawakita
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Publication number: 20230086907Abstract: Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-? dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.Type: ApplicationFiled: August 16, 2022Publication date: March 23, 2023Inventors: Hyunsuk Chun, Sheng Wei Yang, Shams U. Arifeen
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Patent number: 11557526Abstract: Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.Type: GrantFiled: October 1, 2020Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Hyunsuk Chun, Xiaopeng Qu, Chan H. Yoo
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Patent number: 11538762Abstract: Semiconductor devices may include a die including a semiconductor material. The die may include a first active surface including first integrated circuitry on a first side of the die and a second active surface including second integrated circuitry on a second, opposite side of the die. In some embodiments, the die may include two die portions: a first die portion including the first active surface and a second die portion including the second active surface. The first die portion and the second die portion may be joined together with the first active surface facing away from the second active surface.Type: GrantFiled: January 24, 2020Date of Patent: December 27, 2022Assignee: Micron Technology, Inc.Inventor: Hyunsuk Chun
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Publication number: 20220394878Abstract: A semiconductor component system includes a motherboard and a cooling system mounted to the motherboard. The cooling system includes sidewalls projecting from the motherboard. A sub-motherboard extends between the sidewalls and is spaced apart from the motherboard. The sidewalls and the sub-motherboard define a cooling channel over the motherboard. A connector is attached to the sub-motherboard and is configured to receive a semiconductor device daughterboard. The connector has contacts to electrically couple the semiconductor device daughterboard to the sub-motherboard.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Inventors: Xiaopeng Qu, Hyunsuk Chun
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Patent number: 11515171Abstract: This patent application relates to methods and apparatus for temperature modification and reduction of contamination in bonding stacked microelectronic devices with heat applied from a bond head of a thermocompression bonding tool. The stack is substantially enclosed within a skirt carried by the bond head to reduce heat loss and contaminants from the stack, and heat may be added from the skirt.Type: GrantFiled: June 8, 2020Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Xiaopeng Qu, Hyunsuk Chun, Brandon P. Wirz, Andrew M. Bayless