Patents by Inventor Hyunsun AHN

Hyunsun AHN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System on chip including unified input/output memory management unit
    Patent number: 9361239
    Abstract: A system on chip, includes a memory, a bus, a plurality of intellectual property (IP) blocks, and a unified input/output memory management unit (IOMMU) connected between the memory and the bus and configured to determine whether to perform address conversion for a transaction transferred from the bus based on transaction information.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: June 7, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyunsun Ahn
  • Target device providing debugging function and test system comprising the same
    Patent number: 8819506
    Abstract: A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsun Ahn, Jaegon Lee
  • TARGET DEVICE PROVIDING DEBUGGING FUNCTION AND TEST SYSTEM COMPRISING THE SAME
    Publication number: 20140068331
    Abstract: A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.
    Type: Application
    Filed: October 7, 2013
    Publication date: March 6, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyunsun AHN, Jaegon LEE
  • System-on-chip and debugging method thereof
    Patent number: 8656220
    Abstract: A system-on-chip (SoC) includes a core, a plurality of power domain blocks, and a power control circuit including a debug circuit. The power control circuit is configured to control power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegon Lee, Hyunsun Ahn
  • Target device providing debugging function and test system comprising the same
    Patent number: 8555120
    Abstract: A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsun Ahn, Jaegon Lee
  • SYSTEM-ON-CHIP AND DEBUGGING METHOD THEREOF
    Publication number: 20110283141
    Abstract: A system-on-chip (SoC) includes a core, a plurality of power domain blocks, and a power control circuit including a debug circuit. The power control circuit is configured to control power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit.
    Type: Application
    Filed: May 6, 2011
    Publication date: November 17, 2011
    Inventors: JAEGON LEE, Hyunsun Ahn
  • TARGET DEVICE PROVIDING DEBUGGING FUNCTION AND TEST SYSTEM COMPRISING THE SAME
    Publication number: 20110271159
    Abstract: A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.
    Type: Application
    Filed: April 5, 2011
    Publication date: November 3, 2011
    Inventors: Hyunsun AHN, Jaegon Lee
  • SYSTEM ON CHIP INCLUDING UNIFIED INPUT/OUTPUT MEMORY MANAGEMENT UNIT
    Publication number: 20110271075
    Abstract: A system on chip, includes a memory, a bus, a plurality of intellectual property (IP) blocks, and a unified input/output memory management unit (IOMMU) connected between the memory and the bus and configured to determine whether to perform address conversion for a transaction transferred from the bus based on transaction information.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 3, 2011
    Inventor: Hyunsun AHN