Abstract: A method and apparatus for a hybrid network device for performing in a virtual private network (VPN) and a wireless local area network (WLAN) are provided. The hybrid network device comprises a VPN module serving as a VPN hardware accelerator in a WLAN module, which performs in the WLAN, wherein the hybrid network device integrates WLAN and VPN capabilities into one device.

Abstract: Provided is a polarization division multiplexed optical transmission system including a transmitter and a receiver. The transmitter includes a first light source generating an optical signal having a linear polarization state; a second light source generating an optical signal having a horizontal polarization state; a first signal generator receiving a first data stream to modulate the optical signal output from the first light source using an M method; a second signal generator receiving a second data stream to modulate the optical signal output from the second light source using an N method; and a polarization beam combiner (PBC) multiplexing the optical signals that were modulated using the M and N methods while maintaining the linear and horizontal polarization states.

Abstract: An apparatus and a method for generating an optical carrier is disclosed. The apparatus includes: a light source generating a pump light; a SBS generator for stimulated Brillouin scattering the pump light to generate a stokes light from the light source; an attenuator for controlling an amplitude of the pump light from the light source to generate an amplitude controlled pump light; and a detector for heterodyne beating the stokes light and the amplitude controlled pump light to generate an optical carrier.

Abstract: Provided are a clock component generating apparatus using an asymmetrical distortion of NRZ (non-return to zero) signal and an optical transmission and reception system employing it. The clock component generation apparatus can make an NRZ optical signal have large clock component by asymmetrically distorting the rising and the falling waveform of the NRZ signal utilized in an optical communication system. This apparatus includes asymmetrical pull-up circuit for producing a pull-up function and pull-down circuit for pull-down function to thereby generate a clock component in the distorted NRZ data signal. The invention may advantageously be applied to an optical transmission and reception system.

Abstract: An apparatus and a method for generating an optical carrier is disclosed. The apparatus includes: a light source generating a pump light; a SBS generator for stimulated Brillouin scattering the pump light to generate a stokes light from the light source; an attenuator for controlling an amplitude of the pump light from the light source to generate an amplitude controlled pump light; and a detector for heterodyne beating the stokes light and the amplitude controlled pump light to generate an optical carrier.

Abstract: Provided are an apparatus for optimizing bias voltage of an electro-optic modulator, a method therefor, and an optical transmission system using the method. The present research provides a bias voltage optimizing apparatus of an electro-optic modulator that can stabilize bias voltage supplied to the electro-optic modulator through automatic bias voltage initialization control by considering the point that the form of an optical output signal and the intensity of a clock component are changed according to the bias voltage of the electro-optic modulator, a method therefor and an optical transmission system using the method.

Abstract: The present invention relates to none return to zero (NRZ) modulation method. The NRZ optical modulation is performed by combining a clock signal and NRZ data at a sending end and signal distortion capable of being generated when the clock signal and the NRZ data are combined is optimized by controlling the magnitude and phase of the clock signal. At the receiving end, the clock signal is extracted by performing narrow band band-pass filtering of the detected optical signal transmitted from a transmitter and data is recovered using the clock signal. Therefore, a receiver structure for clock extraction is simpler, an error rate of data recovery is lower by clearly extracting the clock signal, and transmission distance of the optical signal is longer.

Abstract: Wireless terminals that are configured to communicate over a wireless local area network include a data processor and at least one MAC control unit that is responsive to the data processor that controls communications with an access point over first and second communications channels. The wireless terminals may further include a first interface between the at least one MAC control unit and the first communications channel and a second interface between the at least one MAC control unit and the second communications channel.

Abstract: A method and circuit for determining correspondences between storage elements of a first circuit model and storage elements of a second circuit model. A first circuit model is received (102) and a second circuit model is received (104). Next, input correspondences (106) and output correspondences (108) between the circuit models are received. Each of the circuit models include a plurality of inputs, a plurality of outputs, a plurality of storage elements, and a plurality of logic functions. Signatures of each uncorresponded storage elements in the first circuit model (110) and the second circuit model (112) are determined. The signatures of the storage elements are compared (114). When a signature of a storage element of the first circuit model compares favorably to a signature of a storage element of the second circuit model, a correspondence is determined between the respective storage elements (116). Compatible cluster analysis may also be used in the method.

Abstract: A method (FIGS. 12-16) and a data processing system (FIG. 4) are used to verify the correct operation of one or more tri-state multiplexers (FIG. 3) located in a circuit model (37). The tri-state multiplexer checker (38) accesses the circuit model (37) and identifies the tri-state multiplexer(s). Once identified these tri-state multiplexers are checked to ensure that: (1) no two or more select/control lines to a tri-state MUX are enabled at a critical point in time wherein tri-state MUX output line contention can occur (i.e. both a logic zero and a logic one are being driven to the MUX output); and (2) that at least one select/control line is enabled during all critical periods of time so that a high impedance (high-Z) state is not propagated incorrectly through the MUX. This checking/verification is performed in a cut-set manner which is iterative and very time efficient when compared to prior methods.