Abstract: A case for a secondary battery, in which an electrode assembly having a structure, in which electrodes and separators are alternately disposed, is accommodated, includes: a first recess part and a second recess part, each of which has a recessed shape; a circumferential part configured to surround a circumference of each of the first recess part and the second recess part when the case is unfolded; and a connection part provided between the first recess part and the second recess part to connect the first recess part to the second recess part, wherein, when the case is unfolded, the connection part has a shape that is recessed from each of the first recess part and the second recess part in one direction.

Abstract: A system including an operating speed detection apparatus, an operating speed detection apparatus and method thereof. In the example method, a received clock signal may be delayed to generate a plurality of delayed clock signals. A plurality of detection signals may be generated based on the plurality of delayed clock signals and the received clock signal. An operating speed (e.g., of a system) may be determined based at least in part on the plurality of detection signals. In an example, the example method may be performed by an operating speed detection apparatus. In another example, the example method may be performed by a system including the operating speed detection apparatus.

Abstract: A microcomputer system includes first and second IP blocks, a multi-port memory, a shared memory field allocated to the second IP block, and a second memory field. A first memory controller is configured to control access to the first and shared memory fields. A second memory controller is configured to control access to the second and shared memory fields. A bus controller operates in response to access request signals provided from the first and second IP blocks. When the second memory controller is in a ready state and the first and second IP blocks request access to the first and shared memory fields, the bus controller provides the first memory controller with access to the access request signal of the first IP block and provides the second memory controller with access to the access request signal of the second IP block.

Abstract: A system including an operating speed detection apparatus, an operating speed detection apparatus and method thereof. In the example method, a received clock signal may be delayed to generate a plurality of delayed clock signals. A plurality of detection signals may be generated based on the plurality of delayed clock signals and the received clock signal. An operating speed (e.g., of a system) may be determined based at least in part on the plurality of detection signals. In an example, the example method may be performed by an operating speed detection apparatus. In another example, the example method may be performed by a system including the operating speed detection apparatus.