Patents by Inventor Hyun-Wook Jung

Hyun-Wook Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135595
    Abstract: The present invention relates to a method and apparatus for encoding a displacement video using image tiling. A method for encoding multi-dimensional data according to an embodiment of the present disclosure may comprise: converting the multi-dimensional data into one or more frames with two-dimensional characteristics; generating one or more frame groups by grouping the one or more frames with pre-configured number units; reconstructing frames belonging to each frame group into a tiled frame; and generating a bitstream by encoding the tiled frame. Here, the tiled frame may be constructed with one or more blocks, and each block may be constructed by rearranging pixels existing at the same location in the frames.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 25, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Da Yun NAM, Hyun Cheol KIM, Jeong Il SEO, Seong Yong LIM, Chae Eun RHEE, Gwang Cheol RYU, Yong Wook SEO, Hyun Min JUNG
  • Patent number: 11937476
    Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: March 19, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Sung An, Sung Ho Kim, Yong Jae Kim, Yun Hwan Park, Yoon Jee Shin, Sug Woo Jung, Hyun Wook Choi
  • Publication number: 20240055575
    Abstract: A method of preparing a negative electrode for a rechargeable lithium battery and a rechargeable lithium battery including the negative electrode, and the method of preparing the negative electrode may include preparing an active material layer on a current collector so that a coated portion in which the active material layer is formed and an uncoated region in which an active material is not formed are alternatively arranged, the active material, wherein the coated portion is formed by coating a first negative active material layer composition having a capillary number of about 0.25 to about 1.50 on the current collector and coating a second negative active material layer composition having a capillary number of about 0.28 to about 1.50 on the first negative active material layer composition.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 15, 2024
    Inventors: Gwangwon PARK, Won-Gi AHN, Min-young JEONG, Taeil LEE, Juhye BAE, Jin Seok PARK, Hyun Wook JUNG, Kwan Young LEE
  • Publication number: 20230361000
    Abstract: A packaging unit for direct cooling of a semiconductor device according to an embodiment includes a substrate made of a material capable of manufacturing the semiconductor device, having a material layer for forming the semiconductor device stacked on one side thereof, and a flow channel through which a cooling fluid flows formed on the other surface thereof to enable direct cooling of the semiconductor device using the cooling fluid, a packaging block disposed at a position spaced apart from the substrate for packaging of the semiconductor device, electrically connected to the semiconductor device using an electrode, and insulated from the semiconductor device using the electrode disposed on an insulating block, and a heat sink unit disposed below the packaging block and including a flow path forming portion in which a flow path communicating with the flow channel of the substrate is formed.
    Type: Application
    Filed: August 9, 2022
    Publication date: November 9, 2023
    Inventors: Hyoung Soon LEE, Min Soo KANG, Hae Cheon KIM, Hyun Wook JUNG, Ho Kyun AHN, Jong Won LIM
  • Patent number: 11779953
    Abstract: A slot die for manufacturing a rechargeable battery electrode includes a first block with a chamber to accommodate an active material slurry, a second block facing and attached to the first block, a shim between the first and second blocks and including facing end portions, and a slot between the first and second blocks, and between the facing end portions, the slot including a first side defined by the first block, and a second side defined by the second block and facing the first side. Each of the end portions of the shim includes a width adjuster protruding to a second reference point from a first reference point in a width direction by a first adjusting width, extending to a third reference point from the second reference point at a first angle with respect to a discharging direction, and having a first adjusting length in the discharging direction.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: October 10, 2023
    Assignees: SAMSUNG SDI CO., LTD., KOREA UNIVERSITY Research and Business Foundation
    Inventors: Won-Gi Ahn, Yongho Kim, Jin Seok Park, Juhye Bae, Hyeri Eom, Min-young Jeong, Hyun Wook Jung
  • Publication number: 20230278019
    Abstract: A catalyst for purifying exhaust gas includes a first catalyst including a first metal oxide on which platinum (Pt) and rhodium (Rh) are supported, and a second catalyst including a second metal oxide on which palladium (Pd) and platinum (Pt) are supported, wherein the first catalyst and the second catalyst are physically mixed.
    Type: Application
    Filed: December 1, 2022
    Publication date: September 7, 2023
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, Korea University Research and Business Foundation
    Inventors: Kwan Young Lee, Dalyoung Yoon, Hyoseong Woo, Eun Jun Lee, Haney Park, Hyun Wook Jung
  • Publication number: 20230256421
    Abstract: Provided is a carbon monoxide and hydrocarbon oxidation catalyst that includes a core-shell nanoparticle including a cobalt (Co) nanoparticle core having a hexahedral shape, and a shell surrounding the cobalt nanoparticle core and including cerium oxide.
    Type: Application
    Filed: October 18, 2022
    Publication date: August 17, 2023
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, Korea University Research and Business Foundation
    Inventors: Kwan-Young Lee, Dalyoung Yoon, Hyun Wook Jung, Haney Park, Eun Jun Lee, Hyoseong Woo
  • Publication number: 20230054026
    Abstract: Provided are a nitride-based high electron mobility transistor having enhanced frequency characteristics and an improved structural stability and manufacturing method thereof. The nitride-based high electron mobility transistor includes a first semiconductor layer and a second semiconductor layer sequentially formed on a substrate, source drain electrodes formed on the second semiconductor layer, a first insulating film formed on the second semiconductor layer and having an opening, a dielectric formed on the first insulating film to surround the opening of the first insulating film, a second insulating film formed on an inner sidewall of the dielectric, and a gate electrode formed on the dielectric to fill the opening of the first insulating film and inside the inner sidewall of the dielectric. A width of the inner sidewall at a bottom end of the dielectric is smaller than a width of the inner sidewall at a top end of the dielectric.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 23, 2023
    Inventors: Hyun Wook JUNG, Seong II KIM, Hae Cheon KIM, Youn Sub NOH, Ho Kyun AHN, Sang Heung LEE, Jong Won LIM, Sung Jae CHANG, II Gyu CHOI
  • Publication number: 20220285244
    Abstract: The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.
    Type: Application
    Filed: December 27, 2021
    Publication date: September 8, 2022
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Il Gyu CHOI, Seong Il KIM, Hae Cheon KIM, Youn Sub NOH, Ho Kyun AHN, Sang Heung LEE, Jong Won LIM, Sung Jae CHANG, Hyun Wook JUNG
  • Publication number: 20220262922
    Abstract: A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 18, 2022
    Inventors: Soo Cheol KANG, Hyun Wook JUNG, Seong Il KIM, Hae Cheon KIM, Youn Sub NOH, Ho Kyun AHN, Sang Heung LEE, Jong Won LIM, Sung Jae CHANG, Il Gyu CHOI
  • Publication number: 20220045679
    Abstract: Provided is a single pole double through (SPDT) switch including a series switching unit including first and second series switching elements commonly connected to a common input port, and a shunt switching unit including a plurality of shunt switching elements connected in parallel to a first signal path connecting the common input port to a first output port and a second signal path connecting the common input port to a second output port, wherein first and second inductors are respectively connected to gate terminals of the first and second series switching elements.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 10, 2022
    Inventors: Youn Sub NOH, Soo Cheol KANG, Seong Il KIM, Hae Cheon KIM, Ho Kyun AHN, Sang Heung LEE, Jong Won LIM, Sung Jae CHANG, Hyun Wook JUNG
  • Publication number: 20220045022
    Abstract: An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 10, 2022
    Inventors: Sang Heung LEE, Soo Cheol KANG, Seong Il KIM, Hae Cheon KIM, Youn Sub NOH, Ho Kyun AHN, Jong Won LIM, Sung Jae CHANG, Hyun Wook JUNG
  • Publication number: 20210151732
    Abstract: A slot die for manufacturing a rechargeable battery electrode includes a first block with a chamber to accommodate an active material slurry, a second block facing and attached to the first block, a shim between the first and second blocks and including facing end portions, and a slot between the first and second blocks, and between the facing end portions, the slot including a first side defined by the first block, and a second side defined by the second block and facing the first side. Each of the end portions of the shim includes a width adjuster protruding to a second reference point from a first reference point in a width direction by a first adjusting width, extending to a third reference point from the second reference point at a first angle with respect to a discharging direction, and having a first adjusting length in the discharging direction.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 20, 2021
    Inventors: Won-Gi AHN, Yongho KIM, Jin Seok PARK, Juhye BAE, Hyeri EOM, Min-young JEONG, Hyun Wook JUNG
  • Patent number: 10525498
    Abstract: A slot coating apparatus having an improved coating bead region is disclosed. An embodiment of the invention provides a slot coating apparatus configured to coat a coating liquid containing a high concentration of particles over a substrate, where the slot coating apparatus includes: a first slot die that is arranged at a downstream side of the coating liquid; a second slot die that is arranged at an upstream side of the coating liquid and is positioned facing the first slot die; a coating bead cover that extends from one side of the first slot die along a movement direction of the substrate; and a pressure adjustment device that is disposed at the second slot die side and is configured to form a pressure gradient between the downstream and the upstream.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 7, 2020
    Assignee: Korea University Research and Businss Foundation
    Inventors: Hyun Wook Jung, Byoung Jin Chun, Kwan Young Lee, Jin Seok Park, Gi Wook Lee, Won Gi Ahn
  • Publication number: 20190160485
    Abstract: A slot coating apparatus having an improved coating bead region is disclosed. An embodiment of the invention provides a slot coating apparatus configured to coat a coating liquid containing a high concentration of particles over a substrate, where the slot coating apparatus includes: a first slot die that is arranged at a downstream side of the coating liquid; a second slot die that is arranged at an upstream side of the coating liquid and is positioned facing the first slot die; a coating bead cover that extends from one side of the first slot die along a movement direction of the substrate; and a pressure adjustment device that is disposed at the second slot die side and is configured to form a pressure gradient between the downstream and the upstream.
    Type: Application
    Filed: June 29, 2018
    Publication date: May 30, 2019
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Hyun Wook JUNG, Byoung Jin Chun, Kwan Young Lee, Jin Seok Park, Gi Wook Lee, Won Gi Ahn
  • Publication number: 20180333684
    Abstract: The present invention relates to a preparation process for a thin film composite (TFC) membrane (hereinafter TFC membrane), and provides a method for the preparation of a membrane through a one-step process using a dual (double layer)-slot coating technique. In the dual (double layer)-slot coating process according to the present invention, a TFC membrane can be prepared by: forming a double-solution layer through a one-step process of performing simultaneous applying/contact of two immiscible solutions, in which two kinds of reactive organic monomers are dissolved, on a porous support; and synthesizing a selective layer through a crosslinking reaction between the organic monomers at an interface of the double layer.
    Type: Application
    Filed: November 24, 2016
    Publication date: November 22, 2018
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Jung-hyun LEE, Hyun Wook JUNG, Sung-Joon PARK, Won-gi AHN, Wanseok CHOI, Yong Woo LEE
  • Patent number: 10134854
    Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun Ahn, Dong Min Kang, Yong-Hwan Kwon, Dong-Young Kim, Seong Il Kim, Hae Cheon Kim, Eun Soo Nam, Jae Won Do, Byoung-Gue Min, Hyung Sup Yoon, Sang-Heung Lee, Jong Min Lee, Jong-Won Lim, Hyun Wook Jung, Kyu Jun Cho
  • Patent number: 9837719
    Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the m
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 5, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong-Young Kim, Dong Min Kang, Seong-Il Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Ho Kyun Ahn, Hyung Sup Yoon, Sang-Heung Lee, Jong Min Lee, Jong-Won Lim, Yoo Jin Jang, Hyun Wook Jung, Kyu Jun Cho, Chull Won Ju
  • Patent number: 9780176
    Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 3, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong Min Lee, Byoung-Gue Min, Hyung Sup Yoon, Dong Min Kang, Dong-Young Kim, Seong-Il Kim, Hae Cheon Kim, Jae Won Do, Ho Kyun Ahn, Sang-Heung Lee, Jong-Won Lim, Hyun Wook Jung, Kyu Jun Cho, Chull Won Ju
  • Publication number: 20170237171
    Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the m
    Type: Application
    Filed: August 5, 2016
    Publication date: August 17, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong-Young KIM, Dong Min KANG, SEONG-IL KIM, Hae Cheon KIM, Jae Won DO, Byoung-Gue MIN, Ho Kyun AHN, Hyung Sup YOON, Sang-Heung LEE, Jong Min LEE, Jong-Won LIM, Yoo Jin JANG, Hyun Wook JUNG, Kyu Jun CHO, Chull Won JU