Abstract: An electronic device includes a communication circuit, a speaker, and a processor. The processor is configured to identify a bitrate of a first audio bitstream received via the communication circuit from an external electronic device. The processor is configured to obtain, in response to the bitrate lower than a reference value, an audio signal by executing a bandwidth extension (BWE) for the first audio bitstream based on at least one coding parameter obtained from a second audio bitstream previously received via the communication circuit from the external electronic device before the first audio bitstream. The processor is configured to obtain, in response to the bitrate higher than or equal to the reference value, the audio signal for the first audio bitstream without executing the BWE. The processor is configured to output, based on the audio signal, audio via the speaker.

Abstract: In a backlight apparatus, a master driving circuit generates a transmission frame including a training period including a clock training pattern and a data period including a plurality of data packets respectively corresponding to the plurality of blocks. A plurality of slave driving circuits correspond to the plurality of blocks, respectively, and are connected to the master driving circuit in a daisy chain structure. Each slave driving circuit receives the transmission frame through the daisy chain structure, recovers a clock based on the clock training pattern, and drives the plurality of light emitting elements included in a corresponding block among the plurality of blocks based on its own data packet among a plurality of data packets.

Abstract: An electronic device includes a display panel that includes a first region including first pixel groups and a second region including second pixel groups, and a compensation circuit. The compensation circuit may receive first image data. The compensation circuit may compensate to generate second image data in response to a determination that the first image data corresponds to at least one of one or more particular first pixel groups that are adjacent to a boundary between the first region and the second region or one or more particular second pixel groups that are adjacent to the boundary. The compensation circuit outputs the second image data to the display panel.

Abstract: A wireless induction heating cooker includes a main body, a lid coupled to the main body, an internal pot stored in the main body, a first power receiving coil placed at a lower portion of an edge area of the internal pot, a lateral surface heating coil placed on an outer circumferential surface of the internal pot and connected with the first power receiving coil, a power transmitting coil provided on one lateral surface of an upper portion of the main body and supplied with electric currents induced to the first power receiving coil, and a second power receiving coil provided on one lateral surface of the lid and supplying electric currents induced by a magnetic field generated in the power transmitting coil to at least one of electronic devices.

Abstract: A display device includes a display panel including an under display camera (UDC) region and a non-UDC region, the UDC region including a plurality of sub-regions, and processing circuitry configured to, receive image data, select at least one first filter from a plurality of filters based on a spatial coordinate value of the received image data, the plurality of filters corresponding to a respective sub-region of the plurality of sub-regions, and perform first pixel rendering for the UDC region based on the at least one first filter and the image data, and the at least one first filter is generated based on a pixel arrangement pattern of the UDC region.

Abstract: One or more examples relate, generally, to an apparatus. The apparatus includes a charged particle source and a charged particle pointer. The charged particle pointer urges charged particles emitted by the charged particle source in a predetermined direction. The charged particle pointer comprises a repeller, and an isolator positioned along a path extending from the repeller in the predetermined direction.

Abstract: A semiconductor package includes an interposer, an electronic device having a first side surface and a second side surface opposite to the first side surface, and including a plurality of memory dies stacked in a vertical direction, at least one first through pipe passing through the electronic device in the vertical direction adjacent to the first side surface, and moving a cooling liquid therein, and a plurality of thermal transmission lines extending in a horizontal direction inside the memory die, and extending in parallel from the first through pipe toward the second side surface.

Abstract: A vehicle body structure may include: front side members extended in a longitudinal direction of the vehicle and provided at opposite sides of the vehicle body structure; a sub-frame that includes: a front cross member and a rear cross member, which are spaced apart from each other, and front side structures extending forward from opposite sides of the sub-frame, where the sub-frame is coupled to the front side members at opposite sides; fender apron members to connect the front side structures to A-pillars of the vehicle body structure; load distribution members coupled to the fender apron members to transmit a load to the fender apron members and to the front side members; and a cross bar extending in the transverse direction while being spaced apart from an upper side of the front cross member of the sub-frame, and having opposite ends coupled to the front side members.

Abstract: A vehicle body structure may include: front side members extended in a longitudinal direction of the vehicle and provided at opposite sides of the vehicle body structure; a sub-frame that includes: a front cross member and a rear cross member, which are spaced apart from each other, and front side structures extending forward from opposite sides of the sub-frame, where the sub-frame is coupled to the front side members at opposite sides; fender apron members to connect the front side structures to A-pillars of the vehicle body structure; load distribution members coupled to the fender apron members to transmit a load to the fender apron members and to the front side members; and a cross bar extending in the transverse direction while being spaced apart from an upper side of the front cross member of the sub-frame, and having opposite ends coupled to the front side members.

Abstract: A parallel imaging (PI) method has been frequently used as a method for shortening an image acquisition time in the MRI field. The PI technique is a method for acquiring data using multi-channel coils, that is, several coils, when acquiring the data in MRI. According to this technique, data, the amount of which is smaller than that when the data is obtained using only one coil, is acquired, and then an image is obtained using coil information. According to an embodiment, a new image reconstruction method is proposed which adopts an expectation maximization (EM) technique that is different from the existing GRAPPA or SENSE technique when an image is obtained using PI data acquired through the radial trajectory.

Abstract: A positron emission tomography (PET)-magnetic resonance imaging (MRI) convergence system. In one aspect, the invention may be a PET-MRI convergence system including: a cylindrical magnet bore which includes an outer wall and an inner wall; a gradient magnet which is disposed adjacent to the inner wall of the magnet bore; a MRI RF coil which is disposed adjacent to the inner wall of the gradient magnet, emits an RF pulse signal and detects MRI data corresponding to the RF pulse signal; and a PET detector which is spaced apart from the MRI RF coil and is disposed adjacent to the inner wall of the gradient magnet, and detects PET data.

Abstract: A method for measuring distortion is provided. In one embodiment, the method for measuring distortion of a current block, used to estimate motion by estimating high-frequency and low-frequency components of the current block, comprises: calculating the sum of distortion values of the high-frequency component of the current block; calculating the sum of first distortion values of the low-frequency component of the current block; calculating a second distortion value of the low-frequency component of the current block; and adding the sum of the distortion values of the high-frequency component and the second distortion value of the low-frequency component of the current block.

Abstract: A positron emission tomography (PET)-magnetic resonance imaging (MRI) convergence system. In one aspect, the invention may be a PET-MRI convergence system including: a cylindrical magnet bore which includes an outer wall and an inner wall; a gradient magnet which is disposed adjacent to the inner wall of the magnet bore; a MRI RF coil which is disposed adjacent to the inner wall of the gradient magnet, emits an RF pulse signal and detects MRI data corresponding to the RF pulse signal; and a PET detector which is spaced apart from the MRI RF coil and is disposed adjacent to the inner wall of the gradient magnet, and detects PET data.

Abstract: Disclosed are a high-order generalized series parallel imaging method for acquiring high spatio-temporal resolution functional magnetic resonance images and a sampling method. The higher-order generalized series parallel imaging method for acquiring high spatio-temporal resolution functional magnetic resonance images includes: performing sampling of an input image in k-space; applying a high-order generalized series (HGS) reconstruction procedure to data acquired as the sampling result to acquire a first reconstructed image; and applying a parallel magnetic resonance reconstruction procedure to the first reconstructed image to acquire a second reconstructed image.

Abstract: A method for measuring distortion is provided. In one embodiment, the method for measuring distortion of a current block, used to estimate motion by estimating high-frequency and low-frequency components of the current block, comprises: calculating the sum of distortion values of the high-frequency component of the current block; calculating the sum of first distortion values of the low-frequency component of the current block; calculating a second distortion value of the low-frequency component of the current block; and adding the sum of the distortion values of the high-frequency component and the second distortion value of the low-frequency component of the current block.

Abstract: Disclosed area high-order generalized series parallel imaging method for acquiring high spatio-temporal resolution functional magnetic resonance images and a sampling method. The higher-order generalized series parallel imaging method for acquiring high spatio-temporal resolution functional magnetic resonance images includes: performing sampling of an input image in k-space; applying a high-order generalized series (HGS) reconstruction procedure to data acquired as the sampling result to acquire a first reconstructed image; and applying a parallel magnetic resonance reconstruction procedure to the first reconstructed image to acquire a second reconstructed image.

Abstract: Object segmentation and tracking are improved by including directional information to guide the placement of an active contour (i.e., the elastic curve or ‘snake’) in estimating the object boundary. In estimating an object boundary the active contour deforms from an initial shape to adjust to image features using an energy minimizing function. The function is guided by external constraint forces and image forces to achieve a minimal total energy of the active contour. Both gradient strength and gradient direction of the image are analyzed in minimizing contour energy for an active contour model.

Abstract: A template is analyzed to determine a step size for searching within a search area. First, the template is padded with pixels to increase its size. Cross-correlation between the padded template and the original template leads to identification of an effective step size. Step sizes for each of horizontal and vertical axes are derived. Windows of the search area, selected based on the step size, then are tested in a fast search stage by correlating the template to the window. Any tested window which has a correlation coefficient exceeding a specific value is a local match. A full search of the vicinity of the local match then is performed for all potential windows within an area bounded by one step to either side of the local match along either axis. The location(s) corresponding to the highest correlation(s) exceeding the threshold value are matches.

Abstract: A template is analyzed to determine a step size for searching within a search area. First, the template is padded with pixels to increase its size. Cross-correlation between the padded template and the original template leads to identification of an effective step size. Step sizes for each of horizontal and vertical axes are derived. Windows of the search area, selected based on the step size, then are tested in a fast search stage by correlating the template to the window. Any tested window which has a correlation coefficient exceeding a specific value is a local match. A full search of the vicinity of the local match then is performed for all potential windows within an area bounded by one step to either side of the local match along either axis. The location(s) corresponding to the highest correlation(s) exceeding the threshold value are matches.

Abstract: The present invention provides a unified image and graphics processing system that provides both image and graphics processing at high speeds. The system includes a parallel vector processing unit, a graphics subsystem, a shared memory and a set of high-speed data buses for connecting all of the other components. Generally, the parallel vector processing unit includes a series of vector processors. Each processor includes a vector address generator for efficient generation of memory addresses for regular address sequences. In order to synchronize and control the vector processors' accesses to shared memory, the parallel vector processing unit includes shared memory access logic. The logic is incorporated into each vector processor. The graphics subsystem includes a series of polygon processors in a pipelined configuration. Each processor is connected in the pipeline by a first-in-first-out (FIFO) buffer for passing data results.