Patents by Inventor I-Chang Shin
I-Chang Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8352888Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: GrantFiled: May 26, 2011Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Patent number: 8214772Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: GrantFiled: May 26, 2011Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20110231804Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: ApplicationFiled: May 26, 2011Publication date: September 22, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20110230998Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: ApplicationFiled: May 26, 2011Publication date: September 22, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Patent number: 7954072Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: GrantFiled: May 15, 2007Date of Patent: May 31, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Patent number: 7685558Abstract: A method for detection and scoring of hotspots in a design layout is provided. A plurality of indices is derived for a plurality of positions in the design layout. The plurality of indices comprises a first index sensitive to energy exposure of the design layout, a second index sensitive to process image formation, and a third index sensitive to mask manufacturing error. The plurality of indices is then analyzed to identify at least one hotspot in the design layout. The at least one hotspot is then prioritized using an integrated hotspot scoring system. The integrated hotspot scoring system prioritizes hotspots based on a look-up table approach or an interpolation approach.Type: GrantFiled: March 6, 2007Date of Patent: March 23, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ming Lai, Ru-Gun Liu, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20070265725Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: ApplicationFiled: May 15, 2007Publication date: November 15, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20070266362Abstract: A method for detection and scoring of hotspots in a design layout is provided. A plurality of indices is derived for a plurality of positions in the design layout. The plurality of indices comprises a first index sensitive to energy exposure of the design layout, a second index sensitive to process image formation, and a third index sensitive to mask manufacturing error. The plurality of indices is then analyzed to identify at least one hotspot in the design layout. The at least one hotspot is then prioritized using an integrated hotspot scoring system. The integrated hotspot scoring system prioritizes hotspots based on a look-up table approach or an interpolation approach.Type: ApplicationFiled: March 6, 2007Publication date: November 15, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ming Lai, Ru-Gun Liu, I-Chang Shin, Yao-Ching Ku, Cliff Hou