Abstract: An electronic device includes: a first substrate; a second substrate, disposed opposite to the first substrate; an insulating layer, disposed on a surface of the first substrate away from the second substrate; and a metal layer, disposed on a surface of the second substrate away from the first substrate, wherein a width of the insulating layer is different from a width of the metal layer.

Abstract: A VCO (voltage-controlled oscillator) includes: a resonant tank having a parallel connection of an inductor, a fixed capacitor, a variable capacitor, a first temperature compensating capacitor, and a second temperature compensating capacitor across a first node and a second node, and configured to establish an oscillation of a first oscillatory voltage at the first node and a second oscillatory voltage at the second node; and a regenerative network placed across the first node and the second node to provide energy to sustain the oscillation. The variable capacitor is controlled by a control voltage, the first temperature compensating capacitor is controlled by a first temperature tracking voltage of a positive temperature coefficient, and the second temperature compensating capacitor is controlled by a second temperature tracking voltage of a negative temperature coefficient.

Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.

Abstract: A VCO (voltage-controlled oscillator) includes: a resonant tank having a parallel connection of an inductor, a fixed capacitor, a variable capacitor, a first temperature compensating capacitor, and a second temperature compensating capacitor across a first node and a second node, and configured to establish an oscillation of a first oscillatory voltage at the first node and a second oscillatory voltage at the second node; and a regenerative network placed across the first node and the second node to provide energy to sustain the oscillation. The variable capacitor is controlled by a control voltage, the first temperature compensating capacitor is controlled by a first temperature tracking voltage of a positive temperature coefficient, and the second temperature compensating capacitor is controlled by a second temperature tracking voltage of a negative temperature coefficient.

Abstract: A semiconductor manufacturing apparatus includes an air distributor inside a chamber. The air distributor includes a first annular plate and a second annular plate disposed in an interior volume of the chamber, and an inner surface of the first annular plate and an inner surface of the second annular plate are connected to each other. A hollow region is defined by the first annular plate and the second annular plate. A gas through hole is extended from an outer surface of the first annular plate to the inner surface of the first annular plate. A plurality of ditches are between the inner surface of the first annular plate and the inner surface of the second annular plate, wherein the ditches are connected with the gas through hole and extended from the gas through hole to the hollow region to blow gas toward the hollow region.

Abstract: A device includes a coil configured in a loop topology starting from a first end and extending to a second end, a pair of inward extension legs configured to extend from the first end and the second end toward an interior side of the coil to a third end and a fourth end, respectively, a pair of outward extension legs configured to extend from the first end and the second end toward an exterior side of the coil to a fifth end and a sixth end, respectively, a first capacitor configured to provide a capacitive coupling between the first end and the second end, a second capacitor configured to provide a capacitive coupling between the third end and the fourth end, and a third capacitor configured to provide a capacitive coupling between the fifth end and the sixth end.

Abstract: A device having a substrate, a dielectric slab attached upon the substrate, a coil including a plurality of metal segments laid out on a first metal layer secured by the dielectric slab, the coil being substantially laterally symmetrical with respect to a central line from a top view perspective, and a shield laid out on a second metal layer secured by the dielectric slab and configured in a tree topology. The shield is substantially laterally symmetrical with respect to the central line from the top view perspective, the tree topology including a plurality of clusters of branches, wherein each of said plurality of clusters of branches is associated with a respective metal segment of the coil and includes a primary branch and at least one set of secondary branches that are branched from the primary branch, parallel to one another, and oriented at a substantially forty-five-degree angle with respect to the respective metal segment from the top view perspective.

Abstract: A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.

Abstract: A device includes a coil configured in a loop topology starting from a first end and extending to a second end, a pair of inward extension legs configured to extend from the first end and the second end toward an interior side of the coil to a third end and a fourth end, respectively, a pair of outward extension legs configured to extend from the first end and the second end toward an exterior side of the coil to a fifth end and a sixth end, respectively, a first capacitor configured to provide a capacitive coupling between the first end and the second end, a second capacitor configured to provide a capacitive coupling between the third end and the fourth end, and a third capacitor configured to provide a capacitive coupling between the fifth end and the sixth end.

Abstract: A device having a substrate, a dielectric slab attached upon the substrate, a coil including a plurality of metal segments laid out on a first metal layer secured by the dielectric slab, the coil being substantially laterally symmetrical with respect to a central line from a top view perspective, and a shield laid out on a second metal layer secured by the dielectric slab and configured in a tree topology. The shield is substantially laterally symmetrical with respect to the central line from the top view perspective, the tree topology including a plurality of clusters of branches, wherein each of said plurality of clusters of branches is associated with a respective metal segment of the coil and includes a primary branch and at least one set of secondary branches that are branched from the primary branch, parallel to one another, and oriented at a substantially forty-five-degree angle with respect to the respective metal segment from the top view perspective.

Abstract: A semiconductor manufacturing apparatus includes an air distributor inside a chamber. The air distributor includes a first annular plate and a second annular plate disposed in an interior volume of the chamber, and an inner surface of the first annular plate and an inner surface of the second annular plate are connected to each other. A hollow region is defined by the first annular plate and the second annular plate. A gas through hole is extended from an outer surface of the first annular plate to the inner surface of the first annular plate. A plurality of ditches are between the inner surface of the first annular plate and the inner surface of the second annular plate, wherein the ditches are connected with the gas through hole and extended from the gas through hole to the hollow region to blow gas toward the hollow region.

Abstract: A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space.

Abstract: Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

Abstract: Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.

Abstract: Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal and a digital N-bit output signal. A local charge-averaging capacitor array (LCACA) is configured to receive the control signal and a reference voltage. An output of the LCACA is coupled to the first low input. The first LCACA is divided into a high sub-array and a low sub-array. The high sub-array is pre-charged to a high reference voltage and the low sub-array is pre-charged to a low reference voltage. The high reference voltage is greater than the low reference voltage.

Abstract: An apparatus for processing a semiconductor wafer includes a factory interface configured to couple with a manufacturing chamber. The factory interface includes a robot; an orienter adjacent to the robot; and a particle remover above the orienter and facing toward a wafer. The particle remover is configured to blow ionized gas on a surface of the wafer so as to remove particles.

Abstract: A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space.

Abstract: A duty cycle detector and calibration system is disclosed. In some embodiments, a duty cycle calibration system includes a first tuning circuit operative to receive an input signal, tune a duty cycle of the input signal to within a first error range, and provide a first output signal. A second tuning circuit tunes a duty cycle of the first output signal to within a second error range and provides a second output signal, where the second error range has more precision than the first error range. A duty cycle detector provides a duty cycle detection signal indicative of a duty cycle of the second output signal, and logic controls the first and second tuning circuits based upon the duty cycle detection signal.

Abstract: A duty cycle detector and calibration system is disclosed. In some embodiments, a duty cycle calibration system includes a first tuning circuit operative to receive an input signal, tune a duty cycle of the input signal to within a first error range, and provide a first output signal. A second tuning circuit tunes a duty cycle of the first output signal to within a second error range and provides a second output signal, where the second error range has more precision than the first error range. A duty cycle detector provides a duty cycle detection signal indicative of a duty cycle of the second output signal, and logic controls the first and second tuning circuits based upon the duty cycle detection signal.

Abstract: A phase locked loop circuit and method for use, in accordance with an embodiment, implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low power.