Abstract: A semiconductor package structure includes a base having a first surface and a second surface opposite thereto, wherein the base comprises a wiring structure, a first electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, a second electronic component disposed over the first surface of the base and electrically coupled to the wiring structure, wherein the first electronic component and the second electronic component are separated by a molding material, a first hole and a second hole formed on the second surface of the base, and a frame disposed over the first surface of the base, wherein the frame surrounds the first electronic component and the second electronic component.

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: An electronic device has a narrow viewing angle state and a wide viewing angle state, and includes a panel and a light source providing a light passing through the panel. In the narrow viewing angle state, the light has a first relative light intensity and a second relative light intensity. The first relative light intensity is the strongest light intensity, the second relative light intensity is 50% of the strongest light intensity, the first relative light intensity corresponds to an angle of 0°, the second relative light intensity corresponds to a half-value angle, and the half-value angle is between ?15° and 15°. In the narrow angle state, a third relative light intensity at each angle between 20° and 60° or each angle between ?20° and ?60° is lower than 20% of the strongest light intensity.

Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.

Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.

Abstract: The present disclosure provides a method for characterizing magnetic properties of a target layer, including providing a first sample having a first structure, providing a second sample having a target layer over the first structure, obtaining a first magnetic property of the first sample, obtaining a second magnetic property of the second sample, and deriving a third magnetic property of the target layer according to the first magnetic property and the second magnetic property.

Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.

Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.

Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.

Abstract: A method of acquiring 3D color information and a 3D color information acquisition apparatus, suitable for obtaining a 3D model of an object, use a pattern light source to acquire topography data for the object. More than 3 basic colors are used to construct the pattern to increase resolution with great number of color combination. According to the color composition and combination, color distortion caused by model projection can be prevented, thereby increasing the reliability and broadening the application of the color acquisition device and method.

Abstract: A method of acquiring 3D color information and a 3D color information acquisition apparatus, suitable for obtaining a 3D model of an object, use a pattern light source to acquire topography data for the object. More than 3 basic colors are used to construct the pattern to increase resolution with great number of color combination. According to the color composition and combination, color distortion caused by model projection can be prevented, thereby increasing the reliability and broadening the application of the color acquisition device and method.

Abstract: An acousto-optic tunable filter (AOTF) utilizing phased array transducers for use as dynamically reconfigurable wavelength division multiplexer. The new type of AOTF has the unique capability of simultaneous and independent selection of multi-wavelength signals and separation into multiple output ports. Preferred embodiments of the AOTF are described that provide increased resolution, narrow channel spacing, lower drive power and reduced coherent crosswalk.

Abstract: A polarization independent acousto-optic tunable filter (PIAOTF) used for multiwavelength switching and routing in wavelength division multiplexing (WDM) networks. In the PIAOTF an incident unpolarized light beam is divided to propagate and to be diffracted along two polarization division branches. By using polarization converters and equal optical paths for the two polarization division channels, a PIAOTF is created which minimizes polarization dependent loss and polarization mode dispersion. Furthermore, a preferred embodiment of the AOTF using an elongated acousto-optic interaction medium is described that provides the additional advantages of narrow bandwidth, lower drive power and easier alignment.

Abstract: An acousto-optic tunable filter based on isotropic acousto-optic diffraction using phased array transducers. The isotropic AOTF provides the advantages of narrow optical passband, low acoustic frequencies, and insensitivity to the input optical polarization. Preferred embodiments of the isotropic AOTFs are described for optimized spectral resolution and diffraction efficiency.

Abstract: An acousto-optic modulator utilizing light diffraction by phased acoustic waves in a birefringent crystal. The wavevector of the resultant acoustic wave is selected so that the tangents to the loci of the wavevectors of the incident and diffracted light are parallel. This provides a large acceptance angle for the acousto-optic modulator. By simultaneously choosing the acoustic wavevector to be tangential to the locus of the diffracted light wavevector, the acousto-optic modulator also achieves increased modulation bandwidth.

Abstract: An apparatus, using two acousto-optical tuned filters for determining the wavelength and angle of approach of a light wave.

Abstract: An electronically tunable optical filter utilizing noncollinear acousto-optic interaction in an acoustically anisotropic, optically birefringent crystal. The directions of optical and acoustic waves are chosen so that the optical ray is collinear with the group velocity of the acoustic wave. The collinear beam configuration provides increased spectral resolution and reduced drive power.

Abstract: A bulk acoustic wave spectrum analyzer and channelizer, using bulk acoustic wave beams in a body of material having the property of conducting bulk acoustic wave beams, including acoustically reflecting surfaces. An input transducer is positioned upon one surface of the body for launching acoustic beams into the body. At least one output transducer set, including a plurality of aligned, juxtaposed electrodes are placed on the outer surfaces of each of the output transducers of the transducer sets.