Patents by Inventor I-Cheng Lin
I-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11974083Abstract: An electronic device including a protection layer, a display panel, and a sound broadcasting element is provided. The protection layer has an inner surface and a side surface directly connected to the inner surface. The display panel is disposed on the inner surface of the protection layer and has a back surface and a side surface directly connected to the back surface. The sound broadcasting element is located adjacent to the side surface of the display panel, and the sound broadcasting element includes a piezoelectric component and a connection component.Type: GrantFiled: January 12, 2023Date of Patent: April 30, 2024Assignee: Innolux CorporationInventors: Tzu-Pin Hsiao, Wei-Cheng Lee, Jiunn-Shyong Lin, I-An Yao
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Publication number: 20240130055Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.Type: ApplicationFiled: March 2, 2023Publication date: April 18, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Cheng HUANG, I-Hung CHIANG, Ji-Yuan SYU, Hsin-Han LIN, Po-Kai CHIU, Kuo-Shu KAO
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Patent number: 11948895Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. Holes are formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material surrounds the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.Type: GrantFiled: July 4, 2022Date of Patent: April 2, 2024Assignee: MEDIATEK INC.Inventors: Tzu-Hung Lin, Chia-Cheng Chang, I-Hsuan Peng, Nai-Wei Liu
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Patent number: 11562403Abstract: A method for profit sharing is provided. The method includes deciding a first sharing rate according to a first event information and a first category information; obtaining a first sharing amount according to the first sharing rate and a first shared profit of the first category information; deciding a second sharing rate according to a second event information and a second category information; obtaining a second sharing amount according to the second sharing rate and a second shared profit of the second category information; deciding a total sharing amount by summing up the first sharing amount and the second sharing amount; and returning the total sharing amount in response to receiving a request from a user device.Type: GrantFiled: December 21, 2020Date of Patent: January 24, 2023Assignee: OBOOK INC.Inventors: Chun-Kai Wang, Chung-Han Hsieh, Hsiu-An Teng, Chih-Yang Liu, Wei-Te Lin, I-Cheng Lin, Shin-Ying Chu, Zih-Hao Lin, Kang-Hsien Chang
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Publication number: 20220398582Abstract: An information delivery method for transferring fund is provided. The information delivery method includes receiving payment information, determining whether a transfer condition is met according to the payment information, in response to determining that the transfer condition is met, obtaining source account information of a source entity and destination account information of a destination entity in the payment information, determining a transfer path according to the source account information of the source entity and the destination account information of the destination entity, and transmitting the payment information from the source entity to the destination entity according to the transfer path.Type: ApplicationFiled: June 11, 2021Publication date: December 15, 2022Applicant: OBOOK INC.Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chih-Yang Liu, Wei-Te Lin, I-Cheng Lin, Jun-De Liao, Kang-Hsien Chang, Chun-Jen Chen, Pei-Hsuan Weng, Yi-Hsuan Lai, Ming-Hung Lin, Shu-Ming Chang, Zih-Hao Lin
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Publication number: 20220198524Abstract: A method for profit sharing is provided. The method includes deciding a first sharing rate according to a first event information and a first category information; obtaining a first sharing amount according to the first sharing rate and a first shared profit of the first category information; deciding a second sharing rate according to a second event information and a second category information; obtaining a second sharing amount according to the second sharing rate and a second shared profit of the second category information; deciding a total sharing amount by summing up the first sharing amount and the second sharing amount; and returning the total sharing amount in response to receiving a request from a user device.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Chun-Kai Wang, Chung-Han Hsieh, Hsiu-An Teng, Chih-Yang Liu, Wei-Te Lin, I-Cheng Lin, Shin-Ying Chu, Zih-Hao Lin, Kang-Hsien Chang
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Patent number: 8300370Abstract: A circuitry of an IC is provided, including a pad, an internal circuit, and an ESD protection circuit. The pad transmits or receives a signal and is coupled to a first node. The internal circuit is coupled to the first node for processing the signal. The ESD protection circuit includes an ESD clamping circuit, a first current limiting and shunting unit and a second current limiting and shunting unit. The ESD clamping circuit is coupled to the first node, for clamping an ESD current flowing through the first node. The first current limiting and shunting unit is through the first node coupled to the pad, for limiting the ESD current and shunting part of the ESD current to a first voltage path. The second current limiting and shunting unit is coupled to the first current limiting and shunting unit, for limiting the ESD current and shunting part of the ESD current to a second voltage path.Type: GrantFiled: November 14, 2008Date of Patent: October 30, 2012Assignee: Mediatek Inc.Inventor: I-Cheng Lin
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Patent number: 8208233Abstract: The present invention provides an ESD protection circuit, including: a first protecting circuit coupled between a first pad and a second pad, the first protecting circuit including a first discharge transistor; and a second protecting circuit coupled to the first pad and the second pad, the second protecting circuit including a second discharge transistor. One of the first and second discharge transistors is a high-voltage component, and the other of the first and second discharge transistors is a low-voltage component.Type: GrantFiled: March 18, 2008Date of Patent: June 26, 2012Assignee: Mediatek Inc.Inventor: I-Cheng Lin
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Patent number: 8023237Abstract: An Electrostatic Discharge protection circuit, the circuit includes a transient detecting circuit, a level adjusting circuit, a discharging circuit, and a sustaining circuit. The transient detecting circuit is coupled to a first pad for detecting an input signal at the first pad to generate a transient signal; the level adjusting circuit is coupled to the transient detecting circuit for adjusting an output voltage at an output terminal of the level adjusting circuit; the discharging circuit is coupled to the first pad and the output terminal of the level adjusting circuit for discharging the input signal of the first pad to a second pad when enabled by the output voltage; and the sustaining circuit is coupled between the level adjusting circuit and the transient detecting circuit, for selectively controlling the level adjusting circuit to sustain an enablement of the discharging circuit according to the transient signal.Type: GrantFiled: September 9, 2008Date of Patent: September 20, 2011Assignee: Mediatek Inc.Inventors: I-Cheng Lin, Tao Cheng
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Publication number: 20110037121Abstract: An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region, wherein a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region.Type: ApplicationFiled: August 16, 2009Publication date: February 17, 2011Inventors: Tung-Hsing Lee, I-Cheng Lin, Wei-Li Tsao
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Patent number: 7830005Abstract: An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.Type: GrantFiled: November 12, 2008Date of Patent: November 9, 2010Assignee: Mediatek Inc.Inventors: Chuan-Cheng Hsiao, Hung-Sung Li, I-Cheng Lin, Che-Yuan Jao
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Publication number: 20100123984Abstract: A circuitry of an IC is provided, including a pad, an internal circuit, and an ESD protection circuit. The pad transmits or receives a signal and is coupled to a first node. The internal circuit is coupled to the first node for processing the signal. The ESD protection circuit includes an ESD clamping circuit, a first current limiting and shunting unit and a second current limiting and shunting unit. The ESD clamping circuit is coupled to the first node, for clamping an ESD current flowing through the first node. The first current limiting and shunting unit is through the first node coupled to the pad, for limiting the ESD current and shunting part of the ESD current to a first voltage path. The second current limiting and shunting unit is coupled to the first current limiting and shunting unit, for limiting the ESD current and shunting part of the ESD current to a second voltage path.Type: ApplicationFiled: November 14, 2008Publication date: May 20, 2010Applicant: MEDIATEK INC.Inventor: I-Cheng Lin
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Publication number: 20100117207Abstract: An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.Type: ApplicationFiled: November 12, 2008Publication date: May 13, 2010Inventors: Chuan-Cheng Hsiao, Hung-Sung Li, I-Cheng Lin, Che-Yuan Jao
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Publication number: 20100061026Abstract: An Electrostatic Discharge protection circuit, the circuit includes a transient detecting circuit, a level adjusting circuit, a discharging circuit, and a sustaining circuit. The transient detecting circuit is coupled to a first pad for detecting an input signal at the first pad to generate a transient signal; the level adjusting circuit is coupled to the transient detecting circuit for adjusting an output voltage at an output terminal of the level adjusting circuit; the discharging circuit is coupled to the first pad and the output terminal of the level adjusting circuit for discharging the input signal of the first pad to a second pad when enabled by the output voltage; and the sustaining circuit is coupled between the level adjusting circuit and the transient detecting circuit, for selectively controlling the level adjusting circuit to sustain an enablement of the discharging circuit according to the transient signal.Type: ApplicationFiled: September 9, 2008Publication date: March 11, 2010Inventors: I-Cheng Lin, Tao Cheng
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Publication number: 20090237846Abstract: The present invention provides an ESD protection circuit, including: a first protecting circuit coupled between a first pad and a second pad, the first protecting circuit including a first discharge transistor; and a second protecting circuit coupled to the first pad and the second pad, the second protecting circuit including a second discharge transistor. One of the first and second discharge transistors is a high-voltage component, and the other of the first and second discharge transistors is a low-voltage component.Type: ApplicationFiled: March 18, 2008Publication date: September 24, 2009Inventor: I-Cheng Lin
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Patent number: 7221027Abstract: An integrated circuit preventing latchup. In the integrated circuit, an internal circuit is disposed in a substrate and has a parasitic SCR structure. At least one ESD protection circuit and active area are disposed on the substrate and coupled to a pad. A first current shunting diode has an anode coupled to the pad and a cathode coupled to a first voltage source. A second current shunting diode has a cathode coupled to the pad and an anode coupled to a second voltage source. Minority-carriers guard rings surround the first current shunting diode and the second shunting diode. Distance between the first and second current shunting diodes and the internal circuit, the active area and the ESD protection circuit exceed 80 ?m.Type: GrantFiled: May 18, 2004Date of Patent: May 22, 2007Assignee: Winbond Electronics CorporationInventor: I-Cheng Lin
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Publication number: 20060027725Abstract: A flag or post support device includes a base having a bottom plate for securing to supporting surfaces, two flaps extended from the bottom plate and each having a number of teeth formed around an orifice, a seat rotatably received between the flaps and having two blocks rotatably secured to the flaps with a fastener, each of the blocks includes a number of teeth for engaging with the teeth of the flaps, and for adjustably securing the blocks of the seat to the base at selected angular positions. A post includes one end received in the seat, and has a passage to receive the fastener, and to solidly secure the post to the seat and thus to the base, and to prevent the post from being disengaged from the seat and the base.Type: ApplicationFiled: August 5, 2004Publication date: February 9, 2006Inventor: I-Cheng Lin
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Patent number: 6988701Abstract: A flag or post support device includes a base having a bottom plate for securing to supporting surfaces, two flaps extended from the bottom plate and each having a number of teeth formed around an orifice, a seat rotatably received between the flaps and having two blocks rotatably secured to the flaps with a fastener, each of the blocks includes a number of teeth for engaging with the teeth of the flaps, and for adjustably securing the blocks of the seat to the base at selected angular positions. A post includes one end received in the seat, and has a passage to receive the fastener, and to solidly secure the post to the seat and thus to the base, and to prevent the post from being disengaged from the seat and the base.Type: GrantFiled: August 5, 2004Date of Patent: January 24, 2006Inventor: I-Cheng Lin
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Publication number: 20050259372Abstract: An integrated circuit preventing latchup. In the integrated circuit, an internal circuit is disposed in a substrate and has a parasitic SCR structure. At least one ESD protection circuit and active area are disposed on the substrate and coupled to a pad. A first current shunting diode has an anode coupled to the pad and a cathode coupled to a first voltage source. A second current shunting diode has a cathode coupled to the pad and an anode coupled to a second voltage source. Minority-carriers guard rings surround the first current shunting diode and the second shunting diode. Distance between the first and second current shunting diodes and the internal circuit, the active area and the ESD protection circuit exceed 80 ?m.Type: ApplicationFiled: May 18, 2004Publication date: November 24, 2005Inventor: I-Cheng Lin