Abstract: A leakage current detection circuit and a fluxgate driver are provided. The leakage current detection circuit is suitable for a fluxgate device. The leakage current detection includes a duty cycle detection circuit, a compensation circuit, and a control signal generation circuit. The duty cycle detection circuit receives a pulse width modulation (PWM) signal from an inverter circuit. The duty cycle detection circuit detects a duty cycle of the PWM signal by sampling the PWM signal with a clock signal to output a count signal. The compensation circuit adjusts a pulse number of the count signal according to an offset signal in a self-test period. The control signal generation circuit calculates an average value of the count signal, and compares the average value with multiple threshold values to respectively generate multiple control signals. The control signals indicate a leakage current state of the fluxgate device.

Abstract: An underwater communication apparatus includes a light transmitting device to transmits a first communication light and a light receiving device to receive a second communication light. Further, a light identification device is used to detect a reference pattern in two dimensions, which is set on a node communication apparatus, to obtain a detection pattern. The light transmitting device and the light receiving device respectively corresponding to the light identification device are set at two relative locations. A power apparatus is used to drive the underwater communication apparatus. A control/monitor apparatus obtains the detection pattern from the light identification device and analyze a difference state between the reference pattern and the detection pattern. According to the difference state, it controls the power apparatus to move the underwater communication apparatus to a location for the detection pattern and the reference pattern being two dimensionally aligned.

Abstract: A chip package structure is provided. The chip package structure comprises a first substrate, a second substrate and a plurality of chips. Therein, one of the chips is connected to the first substrate and electrically connected to the first substrate through a via hole of the first substrate. Thereby, the second substrate does not need the via hole for electrical connection of chips and thus, the surface thereof is adapted to remain intact to allow for the disposition of conductive balls throughout the surface.

Abstract: A chip package structure is provided. The chip package structure comprises a first substrate, a second substrate and a plurality of chips. Therein, one of the chips is connected to the first substrate and electrically connected to the first substrate through a via hole of the first substrate. Thereby, the second substrate does not need the via hole for electrical connection of chips and thus, the surface thereof is adapted to remain intact to allow for the disposition of conductive balls throughout the surface.