Patents by Inventor I-Cheng Wang
I-Cheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152880Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.Type: ApplicationFiled: February 13, 2023Publication date: May 9, 2024Applicant: OBOOK INC.Inventors: Chun-Kai Wang, Chung-Han Hsieh, Chun-Jen Chen, Po-Hua Lin, Wei-Te Lin, Pei-Hsuan Weng, Mei-Su Wang, I-Cheng Lin, Cheng-Wei Chen
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Patent number: 11957064Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: GrantFiled: October 18, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240081157Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240074328Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20220255901Abstract: Devices, systems, methods, and non-transitory computer-readable media for modular network architecture. In one embodiment, a server includes a memory and an electronic processor. The memory stores cloud infrastructure definitions, the cloud infrastructure definitions including a plurality of microservices and security groups that define communication between each of the plurality of microservices. The electronic processor is configured to deploy a first virtual private cloud including a first portion of the plurality of microservices and all of the security groups, deploy a second virtual private cloud including a second portion of the plurality of microservices and the all of the security groups, and deploy a third virtual private cloud including a third portion of the plurality of microservices and the all of the security groups.Type: ApplicationFiled: February 8, 2022Publication date: August 11, 2022Inventors: Ian Cheng, Carlos Eduardo Martell Ayala, I-Cheng Wang, Christopher Zhu Tan, Jonathan Pelletier, Saad Zaamout
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Patent number: 10629519Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.Type: GrantFiled: November 29, 2016Date of Patent: April 21, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
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Patent number: 10573624Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.Type: GrantFiled: November 16, 2018Date of Patent: February 25, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
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Publication number: 20190088626Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU
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Patent number: 10157887Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.Type: GrantFiled: March 9, 2017Date of Patent: December 18, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
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Patent number: 10134683Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.Type: GrantFiled: February 10, 2017Date of Patent: November 20, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu, Yu-Tzu Peng
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Publication number: 20180261573Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.Type: ApplicationFiled: March 9, 2017Publication date: September 13, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU
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Publication number: 20180233457Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.Type: ApplicationFiled: February 10, 2017Publication date: August 16, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tien-Szu CHEN, Kuang-Hsiung CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU, Yu-Tzu PENG
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Publication number: 20180151478Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Inventors: Tien-Szu CHEN, Sheng-Ming WANG, I-Cheng WANG, Wun-Jheng SYU
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Patent number: 7735804Abstract: A sealing valve is disclosed. The valve comprises a valve seat, a power element and an elevation section. The valve seat is provided with through hole from front to rear, and the upper end of the valve seat is connected to a guiding body having a guiding slot and a directional slot. The power element is mounted at the upper end of the valve seat to control the elevating movement of the elevation section. The elevation section is downward extended to mount within a sealing element. The sealing element is driven to the through hole to seal the hole or to be driven away from the through hole, this avoid wearing within the valve seat in the course of sliding.Type: GrantFiled: November 1, 2007Date of Patent: June 15, 2010Assignee: Highlight Tech Corp.Inventors: Ying Chen Chu, I-Cheng Wang, Hsing-Chen Chen, Chien-Chih Yu
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Publication number: 20090114866Abstract: A sealing valve is disclosed. The valve comprises a valve seat, a power element and an elevation section. The valve seat is provided with through hole from front to rear, and the upper end of the valve seat is connected to a guiding body having a guiding slot and a directional slot. The power element is mounted at the upper end of the valve seat to control the elevating movement of the elevation section. The elevation section is downward extended to mount within a sealing element. The sealing element is driven to the through hole to seal the hole or to be driven away from the through hole, this avoid wearing within the valve seat in the course of sliding.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Inventors: Ying Chen Chu, I-Cheng Wang, Hsing-Chen Chen, Chien-Chih Yu