Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

Abstract: A device includes a molding compound encapsulating a first integrated circuit die and a second integrated circuit die; a dielectric layer over the molding compound, the first integrated circuit die, and the second integrated circuit die; and a metallization pattern over the dielectric layer and electrically connecting the first integrated circuit die to the second integrated circuit die. The metallization pattern comprises a plurality of conductive lines. Each of the plurality of conductive lines extends continuously from a first region of the metallization pattern through a second region of the metallization pattern to a third region of the metallization pattern; and has a same type of manufacturing anomaly in the second region of the metallization pattern.

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

Abstract: A device includes a molding compound encapsulating a first integrated circuit die and a second integrated circuit die; a dielectric layer over the molding compound, the first integrated circuit die, and the second integrated circuit die; and a metallization pattern over the dielectric layer and electrically connecting the first integrated circuit die to the second integrated circuit die. The metallization pattern comprises a plurality of conductive lines. Each of the plurality of conductive lines extends continuously from a first region of the metallization pattern through a second region of the metallization pattern to a third region of the metallization pattern; and has a same type of manufacturing anomaly in the second region of the metallization pattern.

Abstract: An electronic device with structure for enhancing antenna performance includes a base cover with rectangle-shaped, a metal plate setting on the base cover, three metal strips, and three conductive patches. The metal plate is rectangle-shaped and includes a first side, a second side, and a third side, the first side is paralleled to the second side. The three metal strips are respectively paralleled to one side of the base cover and the first side, the second side, and the third side of the metal plate to constitute a frame to limit the metal plate. Two of the three conductive patches are electrically contacted with both of the metal plate and the metal strip contacted to the first side, the other conductive patch is electrically contacted with both of the metal plate and the metal strip contacted to the second side.

Abstract: An electronic device with structure for enhancing antenna performance includes a base cover with rectangle-shaped, a metal plate setting on the base cover, three metal strips, and three conductive patches. The metal plate is rectangle-shaped and includes a first side, a second side, and a third side, the first side is paralleled to the second side. The three metal strips are respectively paralleled to one side of the base cover and the first side, the second side, and the third side of the metal plate to constitute a frame to limit the metal plate. Two of the three conductive patches are electrically contacted with both of the metal plate and the metal strip contacted to the first side, the other conductive patch is electrically contacted with both of the metal plate and the metal strip contacted to the second side.

Abstract: An antenna module (20) including an antenna holder (21) and an antenna set (40) is provided. The antenna holder includes a top surface (24) and an external end surface (22). The external end surface includes an upper edge (22a) adjacent to the top surface and a lower edge (22b). The antenna set includes a first antenna (42) and a second antenna (44). The second antenna is longer than the first antenna and is mounted on an upper edge of the external end surface. The second antenna includes a main section (444) mounted on a lower edge of the external end surface, a bent section (446) extending from the main section and is mounted on both the up and the lower edges of the external end surface, and an end section (448) extending from the bent section and is mounted on the top surface of the antenna holder.