Patents by Inventor I-Chia Lin

I-Chia Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11277917
    Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 ?m and 351 ?m.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang, I-Chia Lin
  • Publication number: 20200296836
    Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 ?m and 351 ?m.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventors: Yu-Ju LIAO, Chien-Fan CHEN, Chien-Hao WANG, I-Chia LIN
  • Patent number: 10431554
    Abstract: A semiconductor device package includes: (1) a carrier; (2) an electronic component disposed over a top surface of the carrier; (3) a package body disposed over the top surface of the carrier and covering the electronic component; and (4) a shield layer, including a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer. The first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer. A permeability of the first electrically conductive layer is different from a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 1, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lin, Chieh-Chen Fu, Kuo Hsien Liao, Cheng-Nan Lin
  • Publication number: 20180158783
    Abstract: A semiconductor device package includes: (1) a carrier; (2) an electronic component disposed over a top surface of the carrier; (3) a package body disposed over the top surface of the carrier and covering the electronic component; and (4) a shield layer, including a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer. The first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer. A permeability of the first electrically conductive layer is different from a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.
    Type: Application
    Filed: January 15, 2018
    Publication date: June 7, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Chia LIN, Chieh-Chen FU, Kuo Hsien LIAO, Cheng-Nan LIN
  • Patent number: 9871005
    Abstract: A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top surface of the carrier and covering the electronic component. The semiconductor device package further includes a shield layer, which in turn includes a first electrically conductive layer, a first magnetically permeable layer, and a second electrically conductive layer, where the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive layer and the second electrically conductive layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: January 16, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lin, Chieh-Chen Fu, Kuo Hsien Liao, Cheng-Nan Lin
  • Publication number: 20170200682
    Abstract: A semiconductor device package includes a carrier, an electronic component disposed over a top surface of the carrier, and a package body disposed over the top surface of the carrier and covering the electronic component. The semiconductor device package further includes a shield layer, which in turn includes a first electrically conductive layer, a first magnetically permeable layer, and a second electrically conductive layer, where the first magnetically permeable layer is interposed between and directly contacts the first electrically conductive layer and the second electrically conductive layer.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Inventors: I-Chia LIN, Chieh-Chen FU, Kuo Hsien LIAO, Cheng-Nan LIN
  • Patent number: 9269673
    Abstract: A semiconductor device package includes a substrate, at least one component, a package body, a first conductive layer, a first shielding layer, a second shielding layer and a second conductive layer. The component is disposed on a first surface of the substrate. The package body is disposed on the first surface of the substrate and covers the component. The first conductive layer covers the package body and at least a portion of the substrate. The first shielding layer covers the first conductive layer and has a first thickness and includes a high conductivity material. The second shielding layer covers the first shielding layer and has a second thickness and includes a high permeability material. A ratio of the first thickness to the second thickness being in a range of 0.2 to 3. The second conductive layer covers the second shielding layer.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: February 23, 2016
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Chia Lin, Chieh-Chen Fu, Kuo-Hsien Liao, Cheng-Nan Lin
  • Patent number: 9153542
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: October 6, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Chia Lin, Sheng-Jian Jou, Han-Chee Yen
  • Patent number: 8704341
    Abstract: Semiconductor packages and related methods. The semiconductor package includes a substrate, a semiconductor chip, a package body, a recess and a conductive layer. The substrate includes a grounding element. The semiconductor chip is disposed on the substrate and has a lateral surface and an upper surface. The package body encapsulates the lateral surface of the semiconductor chip. The recess is formed in the package body and exposes the upper surface of the semiconductor chip. The conductive layer covers an outer surface of the package body, the grounding element and the upper surface of the semiconductor chip exposed by the recess to provide both thermal dissipation and EMI shielding for the semiconductor chip.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 22, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Chia Lin, Yu-Chou Tseng, Jin-Feng Yang, Chi-Sheng Chung, Kuo-Hsien Liao
  • Publication number: 20140035097
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first substrate, a second substrate, an interposer substrate, a semiconductor chip, a package body and a first antenna layer. The first substrate comprises a grounding segment. The interposer substrate is disposed between the second substrate and the first substrate. The semiconductor chip is disposed on the second substrate. The package body encapsulates the second substrate, the semiconductor chip and the interposer substrate, and has a lateral surface and an upper surface. The first antenna layer is formed on the lateral surface and the upper surface of the package body, and electrically connected to the grounding segment.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lin, Sheng-Jian Jou, Han-Chee Yen
  • Publication number: 20130307128
    Abstract: Semiconductor packages and related methods. The semiconductor package includes a substrate, a semiconductor chip, a package body, a recess and a conductive layer. The substrate includes a grounding element. The semiconductor chip is disposed on the substrate and has a lateral surface and an upper surface. The package body encapsulates the lateral surface of the semiconductor chip. The recess is formed in the package body and exposes the upper surface of the semiconductor chip. The conductive layer covers an outer surface of the package body, the grounding element and the upper surface of the semiconductor chip exposed by the recess to provide both thermal dissipation and EMI shielding for the semiconductor chip.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Inventors: I-Chia Lin, Yu-Chou Tseng, Jin-Feng Yang, Chi-Sheng Chung, Kuo-Hsien Liao
  • Patent number: 7036649
    Abstract: An auto-bill-dispensing machine is provided. The auto-bill-dispensing machine comprises bill receiver having a plurality of security hooks positioned axially between two positioning plates formed on the two sides of the upper chassis of the bill receiver, and the security hooks are against within a plurality of blocking grooves of the lower chassis to block the bill passage. When the bill enters into the bill passage and being held against on the security hooks, the security hooks of the bill receiver will be out of the blocking groove of the lower chassis to let the bill pass through, and after the bill passes the security hooks, the security device will return to the original position to make the security hooks support within the blocking groove of the lower chassis to prevent the bill being pulled back by a string, a tape, a steel wire or a glued metallic plate.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: May 2, 2006
    Assignee: International Currency Technologies Corporation
    Inventors: Ya-Hui Yang, I-Chia Lin
  • Publication number: 20040212145
    Abstract: An auto-bill-dispensing machine is provided. The auto-bill-dispensing machine comprises bill receiver having a plurality of security hooks positioned axially between two positioning plates formed on the two sides of the upper chassis of the bill receiver, and the security hooks are against within a plurality of blocking grooves of the lower chassis to block the bill passage. When the bill enters into the bill passage and being held against on the security hooks, the security hooks of the bill receiver will be out of the blocking groove of the lower chassis to let the bill pass through, and after the bill passes the security hooks, the security device will return to the original position to make the security hooks support within the blocking groove of the lower chassis to prevent the bill being pulled back by a string, a tape, a steel wire or a glued metallic plate.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 28, 2004
    Inventors: Ya-Hui Yang, I-Chia Lin