Abstract: A method of forming a semiconductor device includes a number of operations. A first metal line is formed in a first inter-metal dielectric (IMD) layer. A second IMD layer is formed over the first IMD layer. A resistive random access memory (RRAM) cell is formed and embedded in the second IMD layer, wherein the RRAM cell includes a bottom electrode, a top electrode and a resistance switchable layer between the top electrode and the bottom electrode, and the first metal line is in contact with the bottom electrode of the RRAM cell. A third IMD layer is formed over the second IMD layer. A second metal line is formed in the third IMD layer, wherein the second metal line is in contact with the top electrode of the RRAM cell.

Abstract: A method of manufacturing a resistive random access memory includes the following steps. An interlayer dielectric layer is formed on a semiconductor substrate. A first conductive material layer is formed in a through hole of the interlayer dielectric layer. At least one interface layer is formed in the through hole. The interface layer covers a bottom surface of the first conductive material layer and exposes a portion of a side surface of the first conductive material layer. A resistive material layer is formed in the through hole and covers the interface layer and the first conductive material layer. A second conductive material layer is formed in the through hole and covers the resistive material layer. A planarization is performed on the first conductive material layer, the resistive material layer and the second conductive material layer to form an embedded resistive random access memory in the through hole.

Abstract: The present disclosure provides a power control method for a microcontroller unit (MCU) and a power control system using the same. The power control method includes after a triggering event of switching CPU frequency occurs, controlling, through a power controller, a low dropout linear regulator (LDO) to output a preset voltage and triggering a clock controller to switch a first central processing unit (CPU) frequency; after the clock controller switches the first CPU frequency, counting, through a clock counter, a number of times of occurrence of a CPU clock within a period to obtain a second CPU frequency; and determining, through the power controller, a corresponding voltage of the second CPU frequency and controlling the LDO to output the corresponding voltage.

Abstract: The present disclosure provides a power control method for a microcontroller unit (MCU) and a power control system using the same. The power control method includes after a triggering event of switching CPU frequency occurs, controlling, through a power controller, a low dropout linear regulator (LDO) to output a preset voltage and triggering a clock controller to switch a first central processing unit (CPU) frequency; after the clock controller switches the first CPU frequency, counting, through a clock counter, a number of times of occurrence of a CPU clock within a period to obtain a second CPU frequency; and determining, through the power controller, a corresponding voltage of the second CPU frequency and controlling the LDO to output the corresponding voltage.

Abstract: A microcontroller and a memory control method for the microcontroller are provided. The microcontroller includes a memory array, multiple memory controllers, and multiple counting controllers. The memory array includes multiple memory segments. The counting controllers count based on a memory clock to generate count values, respectively. When a count value reaches a preset value, a counting controller corresponding to the count value controls a corresponding memory controller to enter a power saving mode. When receiving an operation command, the counting controller resets the count value and controls the corresponding memory controller to enter an operation mode.

Abstract: Disclosed herein is an isolated strain of Roseburia hominis HGM001, which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH under an accession number DSM 34119. A method for producing butyric acid using the isolated strain of Roseburia hominis HGM001, a fermented culture produced by the method, and a method for alleviating an inflammatory disorder using the fermented culture are also disclosed.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A microcontroller and a memory control method for the microcontroller are provided. The microcontroller includes a memory array, multiple memory controllers, and multiple counting controllers. The memory array includes multiple memory segments. The counting controllers count based on a memory clock to generate count values, respectively. When a count value reaches a preset value, a counting controller corresponding to the count value controls a corresponding memory controller to enter a power saving mode. When receiving an operation command, the counting controller resets the count value and controls the corresponding memory controller to enter an operation mode.

Abstract: Disclosed herein is an isolated strain of Roseburia hominis HGM001, which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH under an accession number DSM 34119. A method for producing butyric acid using the isolated strain of Roseburia hominis HGM001, a fermented culture produced by the method, and a method for alleviating an inflammatory disorder using the fermented culture are also disclosed.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A data protection method for a memory includes: detecting a data tampering event to generate a trigger signal; writing a lock signal into the memory during a first time frame based on the lock signal, in which the lock signal is adapted to prevent the protected data from being read; and erasing the protected data based on the lock signal during a second time frame, in which the first time frame precedes the second time frame.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: The present invention relates to the preparation of a liquid fermentate of Sanghuangporus or an extract of Sanghuangporus, compounds identified from the liquid fermentate or the extract, and their novel activity.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.