Patents by Inventor I-Ching Lin
I-Ching Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12156659Abstract: Provided herein is an IVRO surgical guide for positioning a cutting guide on a mandibular ramus such that the mandibular ramus is clamped between a hooked distal end and a slidable component having a curved claw. The cutting guide is placed at a predetermined distance from the posterior edge of the ramus at the mid-waistline of the mandibular ramus along a curvilinear shaft in contact with the lateral surface of the ramus. The cutting guide can accommodate a saw for performing the osteotomy.Type: GrantFiled: January 21, 2022Date of Patent: December 3, 2024Assignee: Vanderbilt UniversityInventors: Susie I Ching Lin, Kevin C Galloway
-
Patent number: 12043843Abstract: The present application provides materials and methods for treating hemoglobinopathies. More specifically, the application provides methods for producing progenitor cells that are genetically modified via genome editing to increase the production of fetal hemoglobin (HbF), as well as modified progenitor cells (including, for example, CD34+ human hematopoietic stem cells) producing increased levels of HbF, and methods of using such cells for treating hemoglobinopathies such as sickle cell anemia and ?-thalassemia.Type: GrantFiled: November 4, 2016Date of Patent: July 23, 2024Assignee: Vertex Pharmaceuticals IncorporatedInventors: Matthew Hebden Porteus, Melanie Ruth Allen, Chad Albert Cowan, Ante Sven Lundberg, Michelle I-Ching Lin, Jeffrey Li, Thao Thi Nguyen
-
Publication number: 20240226339Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting modulating or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.Type: ApplicationFiled: March 21, 2024Publication date: July 11, 2024Applicant: Vertex Pharmaceuticals IncorporatedInventors: Chad Albert Cowan, Ante Sven Lundberg, Tirtha Chakraborty, Michelle I-Ching Lin, Bibhu Prasad Mishra, Elizabeth Paik, Andrew Kernytsky, Todd Douglass Borland
-
Patent number: 11566236Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for creating permanent changes to the genome that can result in at least one deletion, insertion, modulation, or inactivation of a transcriptional control sequence of a BCL11A gene in a cell by genome editing.Type: GrantFiled: February 5, 2019Date of Patent: January 31, 2023Assignee: Vertex Pharmaceuticals IncorporatedInventors: Tirtha Chakraborty, Michelle I-Ching Lin
-
Publication number: 20220233202Abstract: Provided herein is an IVRO surgical guide for positioning a cutting guide on a mandibular ramus such that the mandibular ramus is clamped between a hooked distal end and a slidable component having a curved claw. The cutting guide is placed at a predetermined distance from the posterior edge of the ramus at the mid-waistline of the mandibular ramus along a curvilinear shaft in contact with the lateral surface of the ramus. The cutting guide can accommodate a saw for performing the osteotomy.Type: ApplicationFiled: January 21, 2022Publication date: July 28, 2022Inventors: Susie I Ching Lin, Kevin C. Galloway
-
Publication number: 20220211874Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting, modulating, or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.Type: ApplicationFiled: February 2, 2022Publication date: July 7, 2022Applicant: Vertex Pharmaceuticals IncorporatedInventors: Chad Albert Cowan, Ante Sven Lundberg, Tirtha Chakraborty, Michelle I-Ching Lin, Bibhu Prasad Mishra, Elizabeth Paik, Andrew Kernytsky, Todd Douglass Borland
-
Publication number: 20190284542Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for creating permanent changes to the genome that can result in at least one deletion, insertion, modulation, or inactivation of a transcriptional control sequence of a BCL11A gene in a cell by genome editing.Type: ApplicationFiled: February 5, 2019Publication date: September 19, 2019Applicant: CRISPR Therapeutics AGInventors: Tirtha Chakraborty, Michelle I-Ching Lin
-
Publication number: 20190201553Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting, modulating, or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.Type: ApplicationFiled: March 18, 2019Publication date: July 4, 2019Applicant: CRISPR Therapeutics AGInventors: Chad Albert Cowan, Ante Sven Lundberg, Tirtha Chakraborty, Michelle I-ching Lin, Bibhu Prasad Mishra, Elizabeth Jae-eun Paik, Andrew Kernytsky, Todd Douglas Borland
-
Publication number: 20180273609Abstract: The present application provides materials and methods for treating hemoglobinopathies. More specifically, the application provides methods for producing progenitor cells that are genetically modified via genome editing to increase the production of fetal hemoglobin (HbF), as well as modified progenitor cells (including, for example, CD34+ human hematopoietic stem cells) producing increased levels of HbF, and methods of using such cells for treating hemoglobinopathies such as sickle cell anemia and ?-thalassemia.Type: ApplicationFiled: November 4, 2016Publication date: September 27, 2018Applicant: CRISPR Therapeutics AGInventors: Matthew Hebden PORTEUS, Melanie Ruth ALLEN, Chad Albert COWAN, Ante Sven LUNDBERG, Michelle I-Ching LIN, Jeffrey LI, Thao Thi NGUYEN
-
Patent number: 9236311Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.Type: GrantFiled: January 7, 2015Date of Patent: January 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, I-Ching Lin
-
Publication number: 20150125967Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.Type: ApplicationFiled: January 7, 2015Publication date: May 7, 2015Inventors: Ming-Fa Chen, I-Ching Lin
-
Patent number: 8946084Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.Type: GrantFiled: September 30, 2013Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, I-Ching Lin
-
Publication number: 20140295582Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.Type: ApplicationFiled: September 30, 2013Publication date: October 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Fa Chen, I-Ching Lin
-
Patent number: 8546886Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.Type: GrantFiled: August 24, 2011Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, I-Ching Lin
-
Publication number: 20130049127Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, I-Ching Lin
-
Publication number: 20120258590Abstract: A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.Type: ApplicationFiled: June 19, 2012Publication date: October 11, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Fa CHEN, I-Ching LIN
-
Patent number: 8222139Abstract: A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.Type: GrantFiled: March 30, 2010Date of Patent: July 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, I-Ching Lin
-
Patent number: 8084361Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.Type: GrantFiled: May 30, 2007Date of Patent: December 27, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Cheng Huang, Hua-Shu Wu, Fa-Yuan Chang, I-Ching Lin, Hsi-Lung Lee, Yuan-Hao Chien
-
Publication number: 20110244676Abstract: A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Fa CHEN, I-Ching LIN
-
Publication number: 20080299769Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Cheng Huang, Hua-Shu Wu, Fa-Yuan Chang, I-Ching Lin, Hsi-Lung Lee, Yuan-Hao Chien