Abstract: Provided is a method for preparing a tissue section, including treating a tissue specimen with a clearing agent and at least one labeling agent to obtain a cleared and labeled tissue specimen; generating a three-dimensional (3D) image of the cleared and labeled tissue specimen; performing an image slicing procedure on the 3D image to generate a plurality of two-dimensional (2D) images; identifying a target 2D image among the plurality of 2D images to obtain a distance value of D1, which indicates the distance between the target 2D image and a predetermined surface of the 3D image; preparing a hardened tissue specimen from the cleared and labeled tissue specimen; and cutting the hardened tissue specimen near a predetermined site to obtain a tissue section, wherein the distance between the predetermined site and a surface of the hardened tissue specimen corresponding to the predetermined surface of the 3D image is D1.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

Abstract: A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.

Abstract: The present application provides materials and methods for treating hemoglobinopathies. More specifically, the application provides methods for producing progenitor cells that are genetically modified via genome editing to increase the production of fetal hemoglobin (HbF), as well as modified progenitor cells (including, for example, CD34+ human hematopoietic stem cells) producing increased levels of HbF, and methods of using such cells for treating hemoglobinopathies such as sickle cell anemia and ?-thalassemia.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting modulating or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for creating permanent changes to the genome that can result in at least one deletion, insertion, modulation, or inactivation of a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: Provided herein is an IVRO surgical guide for positioning a cutting guide on a mandibular ramus such that the mandibular ramus is clamped between a hooked distal end and a slidable component having a curved claw. The cutting guide is placed at a predetermined distance from the posterior edge of the ramus at the mid-waistline of the mandibular ramus along a curvilinear shaft in contact with the lateral surface of the ramus. The cutting guide can accommodate a saw for performing the osteotomy.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting, modulating, or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for creating permanent changes to the genome that can result in at least one deletion, insertion, modulation, or inactivation of a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting, modulating, or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: The present application provides materials and methods for treating hemoglobinopathies. More specifically, the application provides methods for producing progenitor cells that are genetically modified via genome editing to increase the production of fetal hemoglobin (HbF), as well as modified progenitor cells (including, for example, CD34+ human hematopoietic stem cells) producing increased levels of HbF, and methods of using such cells for treating hemoglobinopathies such as sickle cell anemia and ?-thalassemia.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.

Abstract: A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.

Abstract: A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.