Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

Abstract: An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors in at least one strong active-region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors in at least one weak active-region structure. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.

Abstract: Provided herein is an IVRO surgical guide for positioning a cutting guide on a mandibular ramus such that the mandibular ramus is clamped between a hooked distal end and a slidable component having a curved claw. The cutting guide is placed at a predetermined distance from the posterior edge of the ramus at the mid-waistline of the mandibular ramus along a curvilinear shaft in contact with the lateral surface of the ramus. The cutting guide can accommodate a saw for performing the osteotomy.

Abstract: Provided herein is an IVRO surgical guide for positioning a cutting guide on a mandibular ramus such that the mandibular ramus is clamped between a hooked distal end and a slidable component having a curved claw. The cutting guide is placed at a predetermined distance from the posterior edge of the ramus at the mid-waistline of the mandibular ramus along a curvilinear shaft in contact with the lateral surface of the ramus. The cutting guide can accommodate a saw for performing the osteotomy.

Abstract: The present application provides materials and methods for treating hemoglobinopathies. More specifically, the application provides methods for producing progenitor cells that are genetically modified via genome editing to increase the production of fetal hemoglobin (HbF), as well as modified progenitor cells (including, for example, CD34+ human hematopoietic stem cells) producing increased levels of HbF, and methods of using such cells for treating hemoglobinopathies such as sickle cell anemia and ?-thalassemia.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting modulating or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for creating permanent changes to the genome that can result in at least one deletion, insertion, modulation, or inactivation of a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: Provided herein is an IVRO surgical guide for positioning a cutting guide on a mandibular ramus such that the mandibular ramus is clamped between a hooked distal end and a slidable component having a curved claw. The cutting guide is placed at a predetermined distance from the posterior edge of the ramus at the mid-waistline of the mandibular ramus along a curvilinear shaft in contact with the lateral surface of the ramus. The cutting guide can accommodate a saw for performing the osteotomy.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting, modulating, or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for creating permanent changes to the genome that can result in at least one deletion, insertion, modulation, or inactivation of a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: Materials and methods for treating a patient with a hemoglobinopathy, both ex vivo and in vivo, and materials and methods for deleting, modulating, or inactivating a transcriptional control sequence of a BCL11A gene in a cell by genome editing.

Abstract: The present application provides materials and methods for treating hemoglobinopathies. More specifically, the application provides methods for producing progenitor cells that are genetically modified via genome editing to increase the production of fetal hemoglobin (HbF), as well as modified progenitor cells (including, for example, CD34+ human hematopoietic stem cells) producing increased levels of HbF, and methods of using such cells for treating hemoglobinopathies such as sickle cell anemia and ?-thalassemia.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: A method includes forming conductive material in a contact hole and a TSV opening, and then performing one step to remove portions of the conductive material outside the contact hole and the TSV opening to leave the conductive material in the contact hole and the TSV opening, thereby forming a contact plug and a TSV structure, respectively. In some embodiments, the removing step is performed by a CMP process.