Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.

Abstract: A processing method of a single crystal material includes the following steps. A single crystal material is provided as an object to be modified. The amorphous phase modification apparatus is used for emitting a femtosecond laser beam to process an internal portion of the object to be modified. The processing includes using a femtosecond laser beam to form a plurality of processing lines in the internal portion of the object to be modified, wherein each of the processing lines include a zigzag pattern processing, and a processing line spacing between the plurality of processing lines is in a range of 200 ?m to 600 ?m, wherein after the object to be modified is processed, a modified layer is formed in the object to be modified. Slicing or separating out a portion in the object to be modified that includes the modified layer.

Abstract: The present invention relates to a temperature control system and a temperature control method for an electronic device-testing apparatus. The temperature control system mainly includes a test socket, a temperature-controlling fluid supply device and a temperature-controlling fluid recovery device. A temperature-controlling fluid is supplied to a chip slot of the test socket by the temperature-controlling fluid supply device and drawn from the chip slot by the temperature-controlling fluid recovery device. In the present invention, the temperature-controlling fluid is forced to flow through the chip slot loaded with an electronic device so as to forcibly exchange heat with the electronic device and components in the chip slot, thereby achieving the constant temperature test. After the test is completed, the temperature-controlling fluid can be effectively recovered so that the contamination of the electronic device or the testing apparatus can be avoided.

Abstract: A liquid cooling system, a liquid cooling method, and an electronic device-testing apparatus having the system are disclosed. When an electronic device is accommodated in a chip slot of a test socket, a cooling liquid supply device supplies a cooling liquid to the chip slot through a fluid inlet portion, and the cooling liquid at least flows over parts of the upper and lower surfaces of the electronic device and then flows out from a fluid outlet portion. The chip slot of the test socket serves as the flow space for the cooling liquid so that the cooling liquid can flow over the upper and lower surfaces of the electronic device, and the electronic device can be immersed in the continuously flowing cooling liquid. The flowing cooling liquid can also take away foreign matter, avoiding the influence of the foreign matter on the test.

Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.

Abstract: An IC design method is provided that includes steps outlined below. A clock tree structure is retrieved from an IC design file. A branch level number of a branch that each of clock units in the clock tree structure locates is determined. A common branch level number of a common branch that closest to each two of the flip-flops is determined. A scan chain structure is retrieved from the IC design file. A wire distance and a clock skew of each two of the flip-flops are determined. A cost is calculated according to the common branch number, the wire distance and the clock skew. An initial point and a terminal point of the flip-flops in the scan chain structure are determined to further calculate a path having a minimum cost. The order of the scan chain structure of the IC design file is updated.

Abstract: The invention discloses a clock tree synthesis method including steps of: determining a driving strength of a clock cell; determining a reserved space corresponding to the clock cell according to the driving strength; generating the clock cell and the reserved space, wherein the reserved space is adjacent to the clock cell; setting a decoupling capacitor filler cell in the reserved space, wherein the area and/or capacitance of the decoupling capacitor filler cell are/is associated with the driving strength; and fixing the attribute(s) of the clock cell and the attribute(s) of the decoupling capacitor filler cell.

Abstract: The invention discloses a clock tree synthesis method including steps of: determining a driving strength of a clock cell; determining a reserved space corresponding to the clock cell according to the driving strength; generating the clock cell and the reserved space, wherein the reserved space is adjacent to the clock cell; setting a decoupling capacitor filler cell in the reserved space, wherein the area and/or capacitance of the decoupling capacitor filler cell are/is associated with the driving strength; and fixing the attribute(s) of the clock cell and the attribute(s) of the decoupling capacitor filler cell.