Abstract: An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.

Abstract: An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.

Abstract: The invention is a novel erase method for erasing flash EEPROM memory devices. A memory cell of such a memory device has a first semiconductor region of one conductivity type formed in a second region of the opposite conductivity type, source and drain regions of the opposite conductivity type formed in the first semiconductor region, and a gate. The second region is formed within a substrate of the one conductivity type. The gate includes a control gate and a floating gate, which retains charge and overlies the first semiconductor region. The erase method of the invention includes the steps of: applying a first voltage of one polarity to the source region and the first and second semiconductor regions; and simultaneously applying a second voltage of the opposite polarity to the gate, whereby any charge on the floating gate tunnels through the floating gate dielectric into both the first region and the source region, thereby removing any charge retained by the floating gate.