Abstract: A networking processor is formed with selected ones of one or more system interfaces, one or more network/intermediate interfaces, a plurality of data link sub-layer control/processing blocks, and a plurality of physical sub-layer coders/decoders and processing units. The elements are provisioned in a combinatorially selectable manner, enabling the single networking processor to be able to selectively facilitate data trafficking in accordance with a selected one of a plurality of protocols. The protocols include at least one each a datacom and a telecom protocol. Accordingly, the network processor supports data traffics spanning local, regional and wide area networks. In one embodiment, the traffic data may be framed or streaming data being transmitted/received in accordance with a selected one of a plurality frame based protocols and a plurality of variants of a synchronous protocol. The frame based protocols may also be frame based protocols encapsulated with the synchronous protocol.

Abstract: A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

Abstract: Methods and apparatus provide single or multi-port, flexible, cost-effective, built-in self-test capabilities for network communications equipment, such as for example switches, and programmably generate, and subsequently analyze, one or more sequences of test packets, wherein the test packets simulate at least two flows of traffic. Such test packets can have programmable headers, payloads, and duty cycle. A line card embodying the present invention may generate its own traffic pattern, which may be similar or identical, to traffic patterns observed on Internet backbones. These traffic patterns may contain a bimodal distribution of control packets interspersed with data packets wherein the control packets and data packets are relatively short and long respectively. A plurality of test packet generators/receivers can be deployed in a network communications device having a plurality of ports. In such a configuration, test generator/receiver is associated with each of the plurality of ports.

Abstract: An optical networking module is formed with an integrated module including optical, optical-electrical and protocol processing components, and complementary software. In one embodiment, the integral protocol processing component is a single ASIC and supports multiple protocols. The module is further equipped with support control electronics in support of control functions to manage the optical, optical-electrical as well as the multi-protocol processing component. The integrated module together with the complementary control software present to an optical networking equipment designer/developer a singular component that handles optical to electrical and electrical to optical conversion, as well as data link and physical sub-layer processing for a selected one of a plurality of datacom and telecom protocols, spanning local, regional as well as wide area networks.

Abstract: Methods and apparatus provide single or multi-port, flexible, cost-effective, built-in self-test capabilities for network communications equipment, such as for example switches, and programmably generate, and subsequently analyze, one or more sequences of test packets, wherein the test packets simulate at least two flows of traffic. Such test packets can have programmable headers, payloads, and duty cycle. A line card embodying the present invention may generate its own traffic pattern, which may be similar or identical, to traffic patterns observed on Internet backbones. These traffic patterns may contain a bimodal distribution of control packets interspersed with data packets wherein the control packets and data packets are relatively short and long respectively. A plurality of test packet generators/receivers can be deployed in a network communications device having a plurality of ports. In such a configuration, test generator/receiver is associated with each of the plurality of ports.

Abstract: An overhead processor processes overhead bytes in a stream of Synchronous Optical Network (SONET) frames in multiple levels. In one embodiment, the overhead processor includes three stages. A first stage provides access for external processing of a first set of overhead bytes in the stream of SONET frames. A second stage is programmable to process a second set of overhead bytes in the stream of SONET frames. A third stage processes a third set of overhead bytes in each frame in the stream of SONET frames.

Abstract: A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

Abstract: A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

Abstract: An optical networking module is formed with an integrated module including optical, optical-electrical and protocol processing components, and complementary software. In one embodiment, the integral protocol processing component is a single ASIC and supports multiple protocols. The module is further equipped with support control electronics in support of control functions to manage the optical, optical-electrical as well as the multi-protocol processing component. The integrated module together with the complementary control software present to an optical networking equipment designer/developer a singular component that handles optical to electrical and electrical to optical conversion, as well as data link and physical sub-layer processing for a selected one of a plurality of datacom and telecom protocols, spanning local, regional as well as wide area networks.

Abstract: A flexible architecture is presented that allows either Synchronous Optical Network (SONET) framing, Optical Transport Network (OTN) framing, or SONET framing followed by OTN framing. The architecture consists of SONET frame processors, OTN frame processors, and a configurable selection network.

Abstract: An overhead processor processes overhead bytes in a stream of Synchronous Optical Network (SONET) frames in multiple levels. In one embodiment, the overhead processor includes three stages. A first stage provides access for external processing of a first set of overhead bytes in the stream of SONET frames. A second stage is programmable to process a second set of overhead bytes in the stream of SONET frames. A third stage processes a third set of overhead bytes in each frame in the stream of SONET frames.

Abstract: In a network apparatus, control logic is provided to preemptively issue pause controls to a sender of network traffic of a link to preemptively regulate a rate the sender may send network traffic of the link. In one embodiment, the pause controls are sent periodically, with each including a pause duration. In one embodiment, at least a selected one of the pause duration and the periodicity of preemptive issuance is determined based at least in part on at least a selected one of a working capacity of storage medium allocated to service the link, a network traffic drain rate of the link, and a fill rate of the input line over which the network traffic of the link is received. In one embodiment, the networking apparatus is an optical networking module with the control logic disposed in a multi-protocol networking processor of the module.

Abstract: A buffering structure including a number of storage structures and associated diversion and/or insertion logic, is provided to facilitate one or more selected ones of post-switching, pre-medium placement, diversion and/or insertion of egress packets, and post-medium extraction, pre-switching, diversion and/or insertion of ingress packets, during data link/physical layer processing of networking traffic. In selected applications, the buffering structure is provided as an integral part of a single ASIC multi-protocol networking processor having data link/physical layer processing components for a number of datacom and telecom protocols. In one of the selected applications, the single ASIC multi-protocol networking processor is employed in conjunction with other optical and electro components to form an integral optical networking module in support of optical-electro networking for the datacom/telecom protocols.

Abstract: An overhead processor processes overhead bytes in a stream of Synchronous Optical Network (SONET) frames in multiple levels. In one embodiment, the overhead processor includes three stages. A first stage provides access for external processing of a first set of overhead bytes in the stream of SONET frames. A second stage is programmable to process a second set of overhead bytes in the stream of SONET frames. A third stage processes a third set of overhead bytes in each frame in the stream of SONET frames.

Abstract: Methods and apparatus provide single or multi-port, flexible, cost-effective, built-in self-test capabilities for network communications equipment, such as for example switches, and programmably generate, and subsequently analyze, one or more sequences of test packets, wherein the test packets simulate at least two flows of traffic. Such test packets can have programmable headers, payloads, and duty cycle. A line card embodying the present invention may generate its own traffic pattern, which may be similar or identical, to traffic patterns observed on Internet backbones. These traffic patterns may contain a bimodal distribution of control packets interspersed with data packets wherein the control packets and data packets are relatively short and long respectively. A plurality of test packet generators/receivers can be deployed in a network communications device having a plurality of ports. In such a configuration, test generator/receiver is associated with each of the plurality of ports.

Abstract: Methods and apparatus provide single or multi-port, flexible, cost-effective, built-in self-test capabilities for network communications equipment, such as for example switches, and programmably generate, and subsequently analyze, one or more sequences of test packets, wherein the test packets simulate at least two flows of traffic. Such test packets can have programmable headers, payloads, and duty cycle. A line card embodying the present invention may generate its own traffic pattern, which may be similar or identical, to traffic patterns observed on Internet backbones. These traffic patterns may contain a bimodal distribution of control packets interspersed with data packets wherein the control packets and data packets are relatively short and long respectively. A plurality of test packet generators/receivers can be deployed in a network communications device having a plurality of ports. In such a configuration, test generator/receiver is associated with each of the plurality of ports.

Abstract: A networking processor is formed with selected ones of one or more system interfaces, one or more network/intermediate interfaces, a plurality of data link sub-layer control/processing blocks, and a plurality of physical sub-layer coders/decoders and processing units. The elements are provisioned in a combinatorially selectable manner, enabling the single networking processor to be able to selectively facilitate data trafficking in accordance with a selected one of a plurality of protocols. The protocols include at least one each a datacom and a telecom protocol. Accordingly, the network processor supports data traffics spanning local, regional and wide area networks. In one embodiment, the traffic data may be framed or streaming data being transmitted/received in accordance with a selected one of a plurality frame based protocols and a plurality of variants of a synchronous protocol. The frame based protocols may also be frame based protocols encapsulated with the synchronous protocol.

Abstract: A flexible architecture is presented that allows either Synchronous Optical Network (SONET) framing, Optical Transport Network (OTN) framing, or SONET framing followed by OTN framing. The architecture consists of SONET frame processors, OTN frame processors, and a configurable selection network.

Abstract: In a network apparatus, control logic is provided to preemptively issue pause controls to a sender of network traffic of a link to preemptively regulate a rate the sender may send network traffic of the link. In one embodiment, the pause controls are sent periodically, with each including a pause duration. In one embodiment, at least a selected one of the pause duration and the periodicity of preemptive issuance is determined based at least in part on at least a selected one of a working capacity of storage medium allocated to service the link, a network traffic drain rate of the link, and a fill rate of the input line over which the network traffic of the link is received. In one embodiment, the networking apparatus is an optical networking module with the control logic disposed in a multi-protocol networking processor of the module.

Abstract: The present invention provides a system and method for converting color data from a higher color resolution to a lower color resolution. Color data is converted by first receiving a plurality of bits representing color data for an image. Next, a subset of pixels represented by the plurality of bits is selected. The color data for each pixel within the selected subset is then divided into least significant bits and most significant bits. Next, the least significant bits for each pixel within the selected subset are compared to a corresponding value in a lookup table. Finally, for each pixel within the selected subset, if the least significant bits are greater than the corresponding value in the lookup table, then the most significant bits are incremented.