Abstract: This invention provides a circuit and a method for re-configuring fuse sets for memory cell array redundancy repair. In addition this invention relates to the use of fuse sets and spare row and column lines in the memory array to repair memory cell defects. Each fuse set can be used for either a row or a column, as needed, during a repair of the memory array. This allows the fuse sets to be allocated freely according to the process defects distribution on the chip and wafer. This results in higher repair efficiency and increased wafer yield.

Abstract: A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.