Patents by Inventor I-Han Huang

I-Han Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250076615
    Abstract: An optical lens assembly includes five lens elements, the five lens elements are, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. Each of the five lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The fourth lens element with positive refractive power has the object-side surface being convex in a paraxial region thereof. The fifth lens element with negative refractive power has the object-side surface being concave in a paraxial region thereof and the image-side surface being concave in a paraxial region thereof.
    Type: Application
    Filed: July 10, 2024
    Publication date: March 6, 2025
    Inventors: I-Chieh CHEN, Hsin-Hsuan HUANG, Yu-Han SHIH
  • Patent number: 12237050
    Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Publication number: 20250056848
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures. The semiconductor nanostructures are beside an epitaxial structure. The method includes forming a dielectric layer over the metal gate stack and the epitaxial structure. The method further includes forming a contact opening in the dielectric layer and forming a protective layer over sidewalls of the contact opening. In addition, the method includes deepening the contact opening so that the contact opening extends into the epitaxial structure after the formation of the protective layer. The method includes forming a conductive contact filling the contact opening.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 13, 2025
    Inventors: Chu-Yuan HSU, Jia-Chuan YOU, Chia-Hao CHANG, Kuo-Cheng CHIANG, I-Han HUANG
  • Publication number: 20250014943
    Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 9, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zheng Yong LIANG, Wei-Ting YEH, I-Han HUANG, Chen-Hao WU, An-Hsuan LEE, Huang-Lin CHAO, Yu-Yun PENG, Keng-Chu LIN
  • Publication number: 20240038719
    Abstract: A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Wen-Ting LAN, I-Han HUANG, Fu-Cheng CHANG, Lin-Yu HUANG, Shi-Ning JU, Kuo-Cheng CHIANG
  • Publication number: 20230402405
    Abstract: The present disclosure describes a method to form a semiconductor structure having an oxide structure on a wafer edge. The method includes forming a device layer on a first substrate, forming an interconnect layer on the device layer, forming an oxide structure on a top surface and along a sidewall surface of the interconnect layer, forming a bonding layer on the oxide structure and the interconnect layer, and bonding the device layer to a second substrate with the bonding layer.
    Type: Application
    Filed: March 20, 2023
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Han Huang, Fu-Cheng Chang, Wen-Ting Lan, Shi Ning Ju, Lin-Yu Huang, Kuo-Cheng Chiang
  • Publication number: 20230142902
    Abstract: A method of manufacturing a semiconductor device structure includes bonding a device substrate to a first de-bond layer. The first de-bond layer is disposed on a first carrier substrate, and the device substrate has a first side facing the first carrier substrate and a second side opposite from the first side. The device substrate has a first width. A front-end-of-line (FEOL) process and a back-end-of-line (BEOL) process are performed on the device substrate. A second carrier substrate having a second de-bond layer is bonded on the second side of the device substrate. The first carrier substrate is removed by removing the first de-bond layer. A width of the device substrate remains the first width after removing the first carrier substrate.
    Type: Application
    Filed: May 20, 2022
    Publication date: May 11, 2023
    Inventors: Shi Ning JU, Wen-Ting LAN, I-Han HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20230005513
    Abstract: The present application discloses an interface transformer. The interface transformer includes a first clock generator, a combinational circuit, and a second clock generator. The first clock generator generates an intermediate clock signal according to an input clock signal. A rising edge of the input clock signal precedes a rising edge of the intermediate clock signal, and a falling edge of the intermediate clock signal precedes a falling edge of the input clock signal. The combinational circuit generates a mask clock signal by delaying the intermediate clock signal. The second clock generator generates a transformed clock signal according to the input clock signal and the mask clock signal. The transformed clock signal has two pulses within a cycle of the input clock signal.
    Type: Application
    Filed: October 14, 2021
    Publication date: January 5, 2023
    Inventors: I-HAN HUANG, CHIH-CHIEH CHIU
  • Publication number: 20220343958
    Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.
    Type: Application
    Filed: July 7, 2022
    Publication date: October 27, 2022
    Inventors: Chih-Chieh CHIU, Chia-En HUANG, Fu-An WU, I-Han HUANG, Jung-Ping YANG
  • Patent number: 11417377
    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Publication number: 20200411071
    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Chih-Chieh CHIU, Chia-En HUANG, Fu-An WU, I-Han HUANG, Jung-Ping YANG
  • Patent number: 10777244
    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Publication number: 20190096458
    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Chih-Chieh CHIU, Chia-En HUANG, Fu-An WU, I-Han HUANG, Jung-Ping YANG
  • Patent number: 10176855
    Abstract: An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Patent number: 10001801
    Abstract: A voltage providing circuit includes a first circuit configured to receive a first input signal and a second input signal and to generate an output signal. The first circuit includes a first transistor configured to switchably couple the second input signal to a first node responsive to the first input signal, a second transistor having a gate terminal coupled with the first node, and a third transistor having a source terminal coupled with a source terminal of the second transistor. The third transistor is configured to set a reference voltage value at the source terminal of the second transistor if the first input signal indicates that the second input signal is pulled from a first voltage value toward a second voltage value and if the second input signal reaches a predetermined voltage value. A second circuit is configured to receive the output signal and to generate an output voltage.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 19, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Han Huang, Chia-En Huang, Chih-Chieh Chiu, Fu-An Wu, Chun-Jiun Dai, Hong-Chen Cheng, Jung-Ping Yang, Cheng Hung Lee
  • Patent number: 9905291
    Abstract: A circuit includes a tracking bit line, a first capacitive circuit, a tracking circuit and a detection circuit. The first capacitive circuit is coupled to the tracking bit line. The first capacitive circuit has a capacitive load on the tracking bit line. The tracking circuit is coupled to the tracking bit line. The tracking circuit being configured to charge or discharge a voltage on the tracking bit line based on a first control signal or the capacitive load. The detection circuit is coupled to the tracking bit line, and is configured to generate a SAE signal responsive to the voltage of the tracking bit line and an inverted first control signal.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Ping Yang, Chih-Chieh Chiu, Fu-An Wu, Chia-En Huang, I-Han Huang
  • Publication number: 20170125086
    Abstract: A circuit includes a tracking bit line, a first capacitive circuit, a tracking circuit and a detection circuit. The first capacitive circuit is coupled to the tracking bit line. The first capacitive circuit has a capacitive load on the tracking bit line. The tracking circuit is coupled to the tracking bit line. The tracking circuit being configured to charge or discharge a voltage on the tracking bit line based on a first control signal or the capacitive load. The detection circuit is coupled to the tracking bit line, and is configured to generate a SAE signal responsive to the voltage of the tracking bit line and an inverted first control signal.
    Type: Application
    Filed: January 6, 2017
    Publication date: May 4, 2017
    Inventors: Jung-Ping YANG, Chih-Chieh CHIU, Fu-An WU, Chia-En HUANG, I-Han HUANG
  • Patent number: 9564193
    Abstract: A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal. The detection unit is coupled to the tracking bit line and configured to generate a sense amplifier enable (SAE) signal in response to the voltage level on the tracking bit line.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Ping Yang, Chih-Chieh Chiu, Fu-An Wu, Chia-En Huang, I-Han Huang
  • Patent number: 9449656
    Abstract: A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a write operation by a header control signal.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Han Huang, Ming-Yi Lee, Chia-En Huang, Fu-An Wu, Jung-Ping Yang, Cheng-Hung Lee
  • Patent number: 9275181
    Abstract: One or more techniques or systems for designing a cell are provided. The cell generally includes one or more transistors, such as a pass gate transistor, a pull up transistor, or a pull down transistor, respectively associated one or more gate to gate distances. In some embodiments, a second gate to gate distance is selected based on a first gate to gate distance. For example, the first gate to gate distance and the second gate to gate distance are associated with a first transistor. In another example, the first gate to gate distance is associated with a first transistor and the second gate to gate distance is associated with a second transistor. In this manner, a cell design is provided to improve a static noise margin (SNM) or a write margin (WM) for the cell, for example.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: March 1, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-En Huang, Yi-Hung Tsai, Chih-Chieh Chiu, Hsiao-Lan Yang, I-Han Huang, Chun-Jiun Dai, Fu-An Wu, Hong-Chen Cheng, Jung-Ping Yang, Cheng Hung Lee