Patents by Inventor Ihao Chen
Ihao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7134106Abstract: Method and system for providing a computer implemented process of performing design for testability analysis and synthesis in an integrated circuit design includes partitioning each logic block in an integrated circuit design based on one or more boundaries of multi-cycle initial setup sequence, excluding one or more partitioned logic blocks with multi-cycle initial setup sequence from valid candidate blocks, selecting a constraint setting set, extracting a subset of constraint settings from the selected constraint setting set, applying the extracted subset of constraint settings to the integrated circuit design, performing design for testability analysis and synthesis on the valid candidate blocks, performing scan cell replacement.Type: GrantFiled: April 9, 2004Date of Patent: November 7, 2006Assignee: Incentia Design Systems Corp.Inventors: Steve C. Huang, Yong Fan, Ihao Chen
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Patent number: 7127695Abstract: For use with a design database and a timing database, a computer implemented process for electronic design automation comprising: receiving a netlist that includes cells interconnected by circuit paths, wherein a plurality of the cells are scan cells connected in at least one scan chain; ordering the scan cells according to a prescribed scan cell ordering rule so as to produce a plurality of ordering relationships among scan cells; assigning respective weights from a first category of one or more weights to respective prescribed scan cell order relationships among scan cells of the netlist; assigning respective weights from a second category of one or more weights to prescribed circuit path relationships among cells of the netlist; and determining a physical placement of the cells of the netlist, including the scan cells, using a cost function that places the cells according to the assigned weights.Type: GrantFiled: May 9, 2003Date of Patent: October 24, 2006Assignee: Incentia Design Systems Corp.Inventors: Steve C. Huang, Ihao Chen
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Patent number: 7080365Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.Type: GrantFiled: March 29, 2002Date of Patent: July 18, 2006Assignee: Sun Microsystems, Inc.Inventors: Jeffrey M. Broughton, Liang T. Chen, William kwei-cheung Lam, Derek E. Pappas, Ihao Chen, Thomas M. McWilliams, Ankur Narang, Jeffrey B. Rubin, Earl T. Cohen, Michael W. Parkin, Ashley N. Saulsbury, Michael S. Ball
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Patent number: 7080334Abstract: A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design, the method comprising: identifying a sequential element associated with a feedback loop in the design; producing a feedback loop signature associated with the feedback loop; wherein the signature includes an indication of feedback element instance type for each feedback element instance in the feedback loop, feedback position at each instance of a feedback element type in the feedback loop and a control signal for each instance of a feedback element type in the feedback loop; evaluating the feedback loop signature so as to generate associated stimulus logic; generating associated load logic; and inserting the generated stimulus logic to control a clock input to the sequential element; and inserting the generated load logic to provide a data input to the sequential element.Type: GrantFiled: May 9, 2003Date of Patent: July 18, 2006Assignee: Incentia Design Systems Corp.Inventors: Yong Fan, Steve C. Huang, Ihao Chen
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Patent number: 7036114Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.Type: GrantFiled: March 29, 2002Date of Patent: April 25, 2006Assignee: Sun Microsystems, Inc.Inventors: Thomas M. McWilliams, Jeffrey B. Rubin, Derek E. Pappas, Oyekunle A. Olukotun, Jeffrey M. Broughton, David R. Emberson, William kwei-cheung Lam, Liang T. Chen, Ihao Chen, Earl T. Cohen, Michael W. Parkin
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Patent number: 6973631Abstract: A computer implemented process of inserting enhanced scan bypass in relation to a bypassed block in an integrated circuit design comprising: receiving an HDL description of the circuit design; wherein the HDL description includes a port specification HDL instruction that specifies port properties of a bypassed block; wherein the HDL description includes an enhanced bypass HDL instruction that specifies how many scan cells to provide per port of the bypassed block in a scan bypass circuit that bypasses the bypassed block; wherein the bypass HDL instruction includes a user-selectable option of at least zero or one or two scan cells per port; in response to the specification HDL instruction and the enhanced bypass HDL instruction, automatically generating a netlist portion that includes scan a bypass circuit that bypasses the bypassed block and that includes the specified number of scan cells per port.Type: GrantFiled: May 9, 2003Date of Patent: December 6, 2005Assignee: Incentia Design Systems Corp.Inventors: Steve C. Huang, Ihao Chen
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Publication number: 20050228616Abstract: Method and system for providing a computer implemented process of performing design for testability analysis and synthesis in an integrated circuit design includes partitioning each logic block in an integrated circuit design based on one or more boundaries of multi-cycle initial setup sequence, excluding the one or more logic blocks with multi-cycle initial setup sequence from valid candidate blocks, selecting a constraint setting set, extracting a subset of constraint settings from the selected constraint setting set, applying the extracted subset of constraint settings to the integrated circuit design, performing design for testability analysis and synthesis on the valid candidate blocks, performing scan cell replacement.Type: ApplicationFiled: April 9, 2004Publication date: October 13, 2005Applicant: Incentia Design Systems, Corp.Inventors: Steve Huang, Yong Fan, Ihao Chen
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Publication number: 20040225978Abstract: A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design comprising: identifying sequential elements and associated feedback loops in the design in the design; for one or more identified sequential elements associated feedback loop, producing a feedback loop signature associated with such sequential element; evaluating the feedback loop signature associated with such sequential element so as to generate associated stimulus logic; breaking at least one feedback loop and removing at least one feedback element associated with such sequential element so as to generate associated load logic; and inserting the generated stimulus logic and the generated load logic in the design to replace the associated feedback loop.Type: ApplicationFiled: May 9, 2003Publication date: November 11, 2004Inventors: Yong Fan, Steve C. Huang, Ihao Chen
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Publication number: 20040015803Abstract: For use with a design database and a timing database, a computer implemented process for electronic design automation comprising: receiving a netlist that includes cells interconnected by circuit paths, wherein a plurality of the cells are scan cells connected in at least one scan chain; ordering the scan cells according to a prescribed scan cell ordering rule so as to produce a plurality of ordering relationships among scan cells; assigning respective weights from a first category of one or more weights to respective prescribed scan cell order relationships among scan cells of the netlist; assigning respective weights from a second category of one or more weights to prescribed circuit path relationships among cells of the netlist; and determining a physical placement of the cells of the netlist, including the scan cells, using a cost function that places the cells according to the assigned weights.Type: ApplicationFiled: May 9, 2003Publication date: January 22, 2004Inventors: Steve C. Huang, Ihao Chen
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Publication number: 20040015788Abstract: A computer implemented process of inserting enhanced scan bypass in relation to a bypassed block in an integrated circuit design comprising: receiving an HDL description of the circuit design; wherein the HDL description includes a port specification HDL instruction that specifies port properties of a bypassed block; wherein the HDL description includes an enhanced bypass HDL instruction that specifies how many scan cells to provide per port of the bypassed block in a scan bypass circuit that bypasses the bypassed block; wherein the bypass HDL instruction includes a user-selectable option of at least zero or one or two scan cells per port; in response to the specification HDL instruction and the enhanced bypass HDL instruction, automatically generating a netlist portion that includes scan a bypass circuit that bypasses the bypassed block and that includes the specified number of scan cells per port.Type: ApplicationFiled: May 9, 2003Publication date: January 22, 2004Inventors: Steve C. Huang, Ihao Chen
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Publication number: 20030188299Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.Type: ApplicationFiled: March 29, 2002Publication date: October 2, 2003Inventors: Jeffrey M. Broughton, Liang T. Chen, William Kwei-Cheung Lam, Derek E. Pappas, Ihao Chen, Thomas M. McWilliams, Ankur Narang, Jeffrey B. Rubin, Earl T. Cohen, Michael W. Parkin, Ashley N. Saulsbury, Michael S. Ball
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Publication number: 20030040896Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.Type: ApplicationFiled: March 29, 2002Publication date: February 27, 2003Inventors: Thomas M. McWilliams, Jeffrey B. Rubin, Derek E. Pappas, Oyekunle A. Olukotun, Jeffrey M. Broughton, David R. Emberson, William kwei-cheung Lam, Liang T. Chen, Ihao Chen, Earl T. Cohen, Michael W. Parkin
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Patent number: 6415420Abstract: A method using at least a portion of a control data flow graph (CDFG) which includes multiple control structures in a computer readable storage medium representing at least a portion of a high level design language (HDL) description of an actual or planned logic circuit to evaluate a need for a sequential state element in the portion of the logic circuit comprising producing a graph structure in the storage medium by providing a path origination node in the storage medium; providing a path destination node in the storage medium; producing respective complete paths between the path origination node and the path destination node by separately concatenating each branch of a first control structure of the CDFG with each branch of a second control structure of the CDFG such that a different respective complete path is produced for each possible combination of a respective branch from the first control structure and a respective branch from the second control structure; associating respective complete paths with aType: GrantFiled: July 15, 1999Date of Patent: July 2, 2002Assignee: Incentia Design Systems, Inc.Inventors: Szu-Tsung Cheng, Ihao Chen, Xuequn Xiang
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Patent number: 6415426Abstract: A novel global placement process and associated computer software are provided for global placement of functional cells of an integrated circuit design. The global placement process is recursive and timing driven. Functional cells are placed according to how that placement is likely to influence signal timing. Also, a novel detailed placement process and associated computer software is provided for detailed placement of functional cells of an integrated circuit design. Target zones are defined which provide indications of the timing impact of functional cell movement. A detailed search for improved cell placements is conducted in which target zones are used to assess the signal timing impact of proposed cell movements. The novel global placement produces a global cell placement result, and the novel detailed placement process produces an improved detailed placement result.Type: GrantFiled: June 2, 2000Date of Patent: July 2, 2002Assignee: Incentia Design Systems, Inc.Inventors: Shing-Chong Chang, Xuequn Xiang, Ihao Chen, Shiang-Tang Huang