Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a select gate, a floating gate, a floating gate cap layer, and an erase gate. The select gate is disposed on the substrate. The floating gate is disposed on the substrate and laterally spaced apart from the select gate, where the floating gate includes top edges forming a closed shape as viewed from a top-down perspective. The floating gate cap layer is disposed on a top surface of the floating gate, where an area of a top surface of the floating gate cap layer is less than an area of a bottom surface of the floating gate. The erase gate is disposed on the floating gate, and one or more of the top edges are covered with the erase gate. A control gate is covered with the erase gate.

Abstract: A non-volatile memory device includes at least one memory cell including a substrate, an assist gate, a byte select gate, a floating gate, and an upper gate. The substrate includes a first doped region and a second doped region. The assist gate is disposed on the substrate and adjacent to the second doped region. The byte select gate is disposed on the substrate and adjacent to the first doped region. The floating gate is disposed on the substrate and between the assist gate and byte select gate, and the floating gate includes an upper edge higher than top surfaces of the assist gate and the byte select gate. The upper gate covers the assist gate and the floating gate, and the upper gate is spaced apart from the byte select gate. The upper edge of the floating gate is embedded in the upper gate.

Abstract: A non-volatile memory device includes a memory cell including a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate and the control gate are disposed on the substrate and laterally spaced apart from each other, and the control gate includes a non-vertical surface. The planar floating gate includes a lateral tip laterally spaced apart from the control gate. The coupling dielectric layer includes a first thickness (T1). The erase gate dielectric layer covers the non-vertical surface of the control gate and the lateral tip of the planar floating gate, and includes a second thickness (T2). The erase gate covers the erase gate dielectric layer and the lateral tip of the planar floating gate. The first thickness and the second thickness satisfy the following relation: (T2)<(T1)<2(T2).

Abstract: A non-volatile memory device includes at least one memory cell and the memory cell includes a substrate, a select gate, a control gate, a floating gate, and an erase gate. The select gate is disposed on the substrate, and the control gate is disposed on the substrate and laterally spaced apart from the select gate. The control gate comprises a non-vertical surface. The floating gate includes a vertical portion and a horizontal portion. The vertical portion disposed between the select gate and the control gate and includes a first top tip laterally spaced apart from the control gate. The horizontal portion is disposed between the substrate and the control gate, where the horizontal portion includes a lateral tip laterally and vertically spaced apart from the control gate. The erase gate covers the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate.

Abstract: A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, an assist gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The assist gate structure is disposed on the substrate. The floating gate includes two opposite first top edges arranged along a first direction, two opposite first sidewalls arranged along the first direction, and two opposite second sidewalls arranged along a second direction different from the first direction. The upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure. Portions of the upper gate structure extend beyond the second sidewalls of the floating gate in the second direction, and the portions of the upper gate structure are disposed above the substrate.

Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

Abstract: A method of manufacturing a non-volatile memory includes the following steps. A stacked structure is formed on a substrate and includes a gate dielectric layer, an assist gate, an insulation layer, and a sacrificial layer stacked in order. A tunneling dielectric layer is formed at one side of the stacked structure. A floating gate is formed on the tunneling dielectric layer. The stacked structure is etched until an uppermost edge of the floating gate is higher than a top surface of the insulation layer. A dielectric material layer is formed to cover sidewalls of the floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the floating gate. An upper gate structure is formed on the etched dielectric material layer, where a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.

Abstract: A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.

Abstract: A non-volatile memory having memory cells is provided. The memory cell includes a source region and a drain region, a select gate, a dummy select gate, a floating gate, an erase gate, and a control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the select gate and the source region, and a top portion of the floating gate has corners in symmetry. The height of the floating gate is lower than the height of the select gate. The erase gate is provided on the source region and covers the corner at the side of the source. The control gate is disposed on the erase gate and the floating gate.

Abstract: A split mechanism for a coaxial photographing device, especially a split mechanism between a photographing unit and a light projection unit of a photographing device used for a full-time surveillance to facilitate an image adjustment or maintenance, uses primarily the photographing unit as a base of support, with the removable light projection unit being assembled coaxially at an image taking end. After the light projection unit is disassembled and changes a position, it can be linked at a constant direction temporarily and can keep operating by using a linking device which is split linearly, such that a calibration light wave needed for adjusting the images can be provided, and the light projection unit can be easily aligned with an axis to be assembled at position upon assembling.

Abstract: A split mechanism for a coaxial photographing device, especially a split mechanism between a photographing unit and a light projection unit of a photographing device used for a full-time surveillance to facilitate an image adjustment or maintenance, uses primarily the photographing unit as a base of support, with the removable light projection unit being assembled coaxially at an image taking end. After the light projection unit is disassembled and changes a position, it can be linked at a constant direction temporarily and can keep operating by using a linking device which is split linearly, such that a calibration light wave needed for adjusting the images can be provided, and the light projection unit can be easily aligned with an axis to be assembled at position upon assembling.