Patents by Inventor I-Huan Huang

I-Huan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240288743
    Abstract: A display device includes a driving substrate, a display medium layer, a protection assembly, a sealant layer, a driving chip, and a conductive substance. The driving substrate has a display area, a sealed area, and a peripheral area. The display medium layer is disposed in the display area of the driving substrate. The protection assembly is located on the display medium layer and includes a cover plate and a transparent conductive layer disposed on the cover plate. The sealant layer is disposed in the sealed area of the driving substrate to as least cover a periphery of the display medium layer. The driving chip is disposed in the peripheral area of the driving substrate. The conductive substance is disposed on the transparent conductive layer of the protection assembly.
    Type: Application
    Filed: February 22, 2024
    Publication date: August 29, 2024
    Applicant: E Ink Holdings Inc.
    Inventors: Yen-Ze Huang, Jen-Shiun Huang, I-Feng Cheng, Kuang-Heng Liang, Ming-Huan Yang
  • Patent number: 9000850
    Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: April 7, 2015
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yao-Cheng Chuang, I-Huan Huang
  • Patent number: 8966192
    Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory. The control unit compares bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 24, 2015
    Assignee: Novatek Microelectronics Corp.
    Inventors: Te-Lin Ping, I-Huan Huang
  • Publication number: 20140253250
    Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 11, 2014
    Inventors: Yao-Cheng Chuang, I-Huan Huang
  • Publication number: 20130275689
    Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the one or more first request instructions and the one or more second request instructions to the memory. The control unit compares bandwidths of the one or more first request instructions with bandwidths of the one or more second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.
    Type: Application
    Filed: June 7, 2013
    Publication date: October 17, 2013
    Inventors: Te-Lin PING, I-Huan HUANG
  • Patent number: 8499126
    Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: July 30, 2013
    Assignee: Novatek Microelectronics Corp.
    Inventors: Te-Lin Ping, I-Huan Huang
  • Publication number: 20110219198
    Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.
    Type: Application
    Filed: March 7, 2011
    Publication date: September 8, 2011
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Te-Lin PING, I-Huan Huang
  • Publication number: 20100299488
    Abstract: A dynamic memory access method includes following steps. First, many data access commands are received. Each of the data access commands accesses a dynamic memory according to a page address and a bank address. Next, whether an access data to be accessed by the corresponding data access command is an instantaneous data or a non-instantaneous data is determined. Then, the page and bank addresses of each of the data access commands are respectively compared with a previously page and bank addresses at a previous time used for accessing the dynamic memory, such that an address hit status is obtained. Next, a service sequence is generated according to whether each of the data access commands is an instantaneous or instantaneous data and the address hit status of the commands. Finally, each of the data access commands is executed to access the dynamic memory sequentially according to the service sequence.
    Type: Application
    Filed: August 3, 2009
    Publication date: November 25, 2010
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Te-Lin Ping, I-Huan Huang